Skip to content
View vishnu-patil01's full-sized avatar
2 followers · 7 following

Block or report vishnu-patil01

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
vishnu-patil01/README.md

https://github.com/vishnu-patil01/vishnu-patil01/blob/main/unnamed.png?raw=true

Hi there 👋 I'm Vishnu Patil

🎓 2nd Year B.Tech (VLSI Design & Technology)
🏫 Shah & Anchor Kutchhi Engineering College
📍 Mumbai University

🔧 Interests:

  • Digital Electronics, VLSI Design
  • HDL Programming (Verilog)
  • Semiconductor Fabrication & Chip Design

📘 Check out my Verilog Projects Repo:
➡️ Verilog Practice

💡 Learning:

  • SystemVerilog
  • Digital System Design
  • FPGA Implementation (Next step!)

📫 Contact:

Pinned Loading

  1. verilog-practice verilog-practice Public

    Beginner-level Verilog HDL programs for digital design and simulation practice.

    Verilog

  2. vishnu-patil01 vishnu-patil01 Public

    Personal GitHub portfolio repository. Get to know more about me, my skills, and the projects I'm building as a B.Tech Electronics (VLSI Design and Technology) student.