feat: implement TraceAlignmentSolver to reduce trace zig-zags (#12)

[MattCrossingham]

This PR implements a as a final post-pack phase in the layout pipeline.

What it does:

• Iteratively nudges components with strong pin-to-pin connections to align them horizontally or vertically.
• Reduces trace 'zig-zags' significantly (verified with SI7021 repro, deviation dropped from 0.45 to 0.05).
• Includes AABB overlap detection to ensure nudges do not introduce new component overlaps.
• Prioritizes nudging 'leaf' components (fewer pins) to maintain the primary layout of large chips.

Fixes #12. /claim #12

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