feat: add TraceAlignmentSolver to reduce trace zig-zag (#12)#97
Open
chenchong0215 wants to merge 2 commits into
Open
feat: add TraceAlignmentSolver to reduce trace zig-zag (#12)#97chenchong0215 wants to merge 2 commits into
chenchong0215 wants to merge 2 commits into
Conversation
…ayouts Addresses issue tscircuit#12 - improves schematic layout by aligning strongly-connected pin pairs after partition packing. After PartitionPackingSolver snaps chips to a grid, pins on adjacent chips often have small off-axis deltas that create visible zig-zag traces. TraceAlignmentSolver runs as a post-pack phase that: - Identifies all strong pin connections from pinStrongConnMap - Computes per-connection zig-zag (off-axis delta between connected pins) - Nudges chip positions to minimize zig-zag using average alignment displacement - Rejects nudges that would cause chip overlaps (AABB collision detection) - Falls back to single-axis nudges if combined nudge causes overlap - Requires minimum improvement threshold to accept any nudge Results: - SI7021 repro: 51.7% zig-zag reduction (0.399 → 0.199) - RP2040Circuit: zig-zag reduced to 0.000 in pipeline integration - No new overlaps introduced - All existing tests pass (9 pass, 1 skip, 0 fail) Pipeline integration: runs as final phase after PartitionPackingSolver. /claim tscircuit#12
|
@chenchong0215 is attempting to deploy a commit to the tscircuit Team on Vercel. A member of the Team first needs to authorize it. |
- Make maxNudge/minImprovement/passes optional in TraceAlignmentSolverInput - Add null check for placement2 in wouldOverlap() - Change buildStrongConnectionPairs/computeWorldPinPos from private to public - Apply biome formatting
Author
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
/claim #12
Problem
Issue #12 asks to improve the schematic layout shown in #11 (SI7021). After
PartitionPackingSolversnaps chips to a packing grid, pins on adjacent chips often have small off-axis deltas that create visible zig-zag traces in the schematic.Concrete numbers from the SI7021 repro:
Solution
Add
TraceAlignmentSolveras a post-pack pipeline phase that nudges chip positions to align strongly-connected pin pairs.How it works
pinStrongConnMapPipeline position
Results
Tests
Differentiation vs other PRs
Files touched
lib/solvers/TraceAlignmentSolver/TraceAlignmentSolver.ts(new)lib/solvers/LayoutPipelineSolver/LayoutPipelineSolver.ts(register phase)tests/TraceAlignmentSolver/TraceAlignmentSolver01.test.ts(new)tests/TraceAlignmentSolver/TraceAlignmentSolverPipeline.test.ts(new)