feat: deterministic row layout for decoupling capacitor partitions

[SealKan]

Fixes #15
/claim #15

What

When SingleInnerPartitionPackingSolver processes a partition with
partitionType="decoupling_caps", it now bypasses PackSolver2
entirely and places all capacitors in a deterministic horizontal row
centered at the origin.

How

Added createDecouplingCapsRowLayout() in
lib/solvers/PackInnerPartitionsSolver/SingleInnerPartitionPackingSolver.ts:

• Chips sorted by natural/numeric chip ID (C1, C2, C10 — not lexicographic C1, C10, C2) using Intl.Collator({numeric:true})
• Centered row: cursor = -totalWidth/2, each cap placed at cursor + width/2, then cursor += width + gap
• Gap: uses decouplingCapsGap if present, falls back to chipGap
• Rotation priority: 0 > 180 > 90 > 270 — prefers portrait axis; when 90/270 is chosen, size.y is used as the row-spacing width
• PackSolver2 is never instantiated: activeSubSolver stays null

Layout comparison

Before/After Visual Demo

Before (PackSolver2): caps placed at arbitrary x/y positions, no stable order.

After (createDecouplingCapsRowLayout):

C7:  x=-0.944, y=0.000, rot=0°
C8:  x=-0.315, y=0.000, rot=0°
C9:  x=0.314,  y=0.000, rot=0°
C10: x=0.943,  y=0.000, rot=0°
→ clean row, all y=0, natural sort, centered at origin

Tests

6 new tests in tests/PackInnerPartitionsSolver/SingleInnerPartitionPackingSolver.test.ts:

1. All chips on y=0, left-to-right order
2. Natural sort: C1 < C2 < C10 (not C1 < C10 < C2)
3. Exact positions with decouplingCapsGap=0.25
4. Falls back to chipGap when decouplingCapsGap absent
5. 90/270 rotation swaps width dimension correctly
6. activeSubSolver is null (PackSolver2 never runs)

All 23 existing tests continue to pass.

[vercel]

@SealKan is attempting to deploy a commit to the tscircuit Team on Vercel.

A member of the Team first needs to authorize it.