[Fix] Add specialized linear layout for decoupling capacitor partitions

[adminlip]

What

Added DecouplingCapsPackingSolver — a specialized solver that creates optimized linear layouts for decoupling capacitor partitions.

Why

Decoupling capacitors need a different packing strategy than regular chip partitions. They should be arranged in a horizontal line near their associated IC, sorted by net connection proximity to the IC pins, for optimal routing and minimal trace length.

Fixes #15

How

• New DecouplingCapsPackingSolver: Dedicated solver for partitionType: "decoupling_caps" partitions

  • Identifies the main IC chip (non-capacitor) in the partition
  • Sorts decoupling caps by their connected pin proximity on the main chip
  • Places caps in a horizontal line below the main chip, aligned by net proximity
  • Supports decouplingCapsGap parameter for spacing control
  • Falls back to simple horizontal layout when no main chip exists

• Updated PackInnerPartitionsSolver: Routes decoupling_caps partitions to the new solver instead of SingleInnerPartitionPackingSolver

• Added 3 comprehensive tests covering:

  • Linear layout with main chip + caps
  • Caps-only partition (no main chip)
  • Custom decouplingCapsGap parameter

Testing

bun test tests/DecouplingCapsPackingSolver.test.ts     # 3 pass
bun test tests/ChipPartitionsSolver.test.ts              # 4 pass
bun test tests/IdentifyDecouplingCapsSolver/             # 1 pass

All core tests pass. 9 pre-existing failures are unrelated @tscircuit/core dependency issues.

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