SPI master and SPI slave for FPGA written in VHDL

Customizable multi chip select supporting Serial Peripheral Interface master.

A hands-on implementation of physical design for a Serial Peripheral Interface (SPI) controller — progressing from RTL Verilog through synthesis, placement, static timing analysis, routing, DRC, LVS, and GDSII generation using the open-source Qflow EDA toolchain with OSU018 standard cell library.