This project implements a Reduced Instruction Set Computer (RISC) using SystemVerilog and can be tested using the Intel DE1-SoC development board. The RISC machine can execute a set of instructions from the ARMv7 Instruction Set Architecture (ISA). It contains a datapath, finite state machine controller, and support for read-write memory.
This project was done in collaboration with my lab partner, Jackson Rockford, for CPEN 211: Introduction to Microcomputers.
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