Remove bare-metal dependency

cortex-m/Cargo.toml

@@ -13,13 +13,13 @@ links = "cortex-m"  # prevent multiple versions of this crate to be linked toget
 rust-version = "1.85"
 
 [dependencies]
-bare-metal = { version = "0.2.4", features = ["const-fn"] }
 critical-section = "1.0.0"
 volatile-register = "0.2.2"
 bitfield = "0.13.2"
 eh0 = { package = "embedded-hal", version = "0.2.4" }
 eh1 = { package = "embedded-hal", version = "1.0.0" }
 cortex-m-macros = { path = "macros", version = "=0.1.0" }
+cortex-m-types = { path = "../cortex-m-types", version = "0.1" }
 
 [dependencies.serde]
 version = "1"

cortex-m/src/interrupt.rs

@@ -1,11 +1,11 @@
 //! Interrupts
 
-pub use bare_metal::{CriticalSection, Mutex, Nr};
 #[cfg(cortex_m)]
 use core::arch::asm;
 #[cfg(cortex_m)]
 use core::sync::atomic::{Ordering, compiler_fence};
 use cortex_m_macros::asm_cfg;
+use critical_section::CriticalSection;
 
 /// Trait for enums of external interrupt numbers.
 ///
@@ -21,19 +21,23 @@ use cortex_m_macros::asm_cfg;
 /// and must always return the same value (do not change at runtime).
 ///
 /// These requirements ensure safe nesting of critical sections.
+#[deprecated(
+    since = "0.8.0",
+    note = "Implement the cortex_m_types::InterruptNumber trait instead"
+)]
 pub unsafe trait InterruptNumber: Copy {
     /// Return the interrupt number associated with this variant.
     ///
     /// See trait documentation for safety requirements.
     fn number(self) -> u16;
 }
 
-/// Implement InterruptNumber for the old bare_metal::Nr trait.
-/// This implementation is for backwards compatibility only and will be removed in cortex-m 0.8.
-unsafe impl<T: Nr + Copy> InterruptNumber for T {
+// This trait is only here for backwards compatibility.
+#[allow(deprecated)]
+unsafe impl<T: cortex_m_types::InterruptNumber> InterruptNumber for T {
     #[inline]
     fn number(self) -> u16 {
-        self.nr() as u16
+        <Self as cortex_m_types::InterruptNumber>::number(self) as u16
     }
 }
 

cortex-m/src/lib.rs

@@ -97,7 +97,6 @@
 #[cfg(all(feature = "cm7-r0p1", not(armv7em)))]
 compile_error!("The feature \"cm7-r0p1\" is only compatible with the armv7em target");
 
-extern crate bare_metal;
 extern crate volatile_register;
 
 #[macro_use]

cortex-m/src/peripheral/nvic.rs

@@ -1,10 +1,10 @@
 //! Nested Vector Interrupt Controller
 
+use cortex_m_types::InterruptNumber;
 use volatile_register::RW;
 #[cfg(not(armv6m))]
 use volatile_register::{RO, WO};
 
-use crate::interrupt::InterruptNumber;
 use crate::peripheral::NVIC;
 
 /// Register block
@@ -101,7 +101,7 @@ impl NVIC {
         let nr = interrupt.number();
 
         unsafe {
-            self.stir.write(u32::from(nr));
+            self.stir.write(nr as u32);
         }
     }
 
@@ -113,7 +113,7 @@ impl NVIC {
     {
         let nr = interrupt.number();
         // NOTE(unsafe) this is a write to a stateless register
-        unsafe { (*Self::PTR).icer[usize::from(nr / 32)].write(1 << (nr % 32)) }
+        unsafe { (*Self::PTR).icer[nr / 32].write(1 << (nr % 32)) }
     }
 
     /// Enables `interrupt`
@@ -127,7 +127,7 @@ impl NVIC {
         unsafe {
             let nr = interrupt.number();
             // NOTE(ptr) this is a write to a stateless register
-            (*Self::PTR).iser[usize::from(nr / 32)].write(1 << (nr % 32))
+            (*Self::PTR).iser[nr / 32].write(1 << (nr % 32))
         }
     }
 
@@ -145,7 +145,7 @@ impl NVIC {
         {
             let nr = interrupt.number();
             // NOTE(unsafe) atomic read with no side effects
-            unsafe { (*Self::PTR).ipr[usize::from(nr)].read() }
+            unsafe { (*Self::PTR).ipr[nr].read() }
         }
 
         #[cfg(armv6m)]
@@ -168,7 +168,7 @@ impl NVIC {
         let mask = 1 << (nr % 32);
 
         // NOTE(unsafe) atomic read with no side effects
-        unsafe { ((*Self::PTR).iabr[usize::from(nr / 32)].read() & mask) == mask }
+        unsafe { ((*Self::PTR).iabr[nr / 32].read() & mask) == mask }
     }
 
     /// Checks if `interrupt` is enabled
@@ -181,7 +181,7 @@ impl NVIC {
         let mask = 1 << (nr % 32);
 
         // NOTE(unsafe) atomic read with no side effects
-        unsafe { ((*Self::PTR).iser[usize::from(nr / 32)].read() & mask) == mask }
+        unsafe { ((*Self::PTR).iser[nr / 32].read() & mask) == mask }
     }
 
     /// Checks if `interrupt` is pending
@@ -194,7 +194,7 @@ impl NVIC {
         let mask = 1 << (nr % 32);
 
         // NOTE(unsafe) atomic read with no side effects
-        unsafe { ((*Self::PTR).ispr[usize::from(nr / 32)].read() & mask) == mask }
+        unsafe { ((*Self::PTR).ispr[nr / 32].read() & mask) == mask }
     }
 
     /// Forces `interrupt` into pending state
@@ -206,7 +206,7 @@ impl NVIC {
         let nr = interrupt.number();
 
         // NOTE(unsafe) atomic stateless write; ICPR doesn't store any state
-        unsafe { (*Self::PTR).ispr[usize::from(nr / 32)].write(1 << (nr % 32)) }
+        unsafe { (*Self::PTR).ispr[nr / 32].write(1 << (nr % 32)) }
     }
 
     /// Sets the "priority" of `interrupt` to `prio`
@@ -230,7 +230,7 @@ impl NVIC {
             #[cfg(not(armv6m))]
             {
                 let nr = interrupt.number();
-                self.ipr[usize::from(nr)].write(prio)
+                self.ipr[nr].write(prio)
             }
 
             #[cfg(armv6m)]
@@ -254,7 +254,7 @@ impl NVIC {
         let nr = interrupt.number();
 
         // NOTE(unsafe) atomic stateless write; ICPR doesn't store any state
-        unsafe { (*Self::PTR).icpr[usize::from(nr / 32)].write(1 << (nr % 32)) }
+        unsafe { (*Self::PTR).icpr[nr / 32].write(1 << (nr % 32)) }
     }
 
     #[cfg(armv6m)]
@@ -263,7 +263,7 @@ impl NVIC {
     where
         I: InterruptNumber,
     {
-        usize::from(interrupt.number()) / 4
+        interrupt.number() / 4
     }
 
     #[cfg(armv6m)]
@@ -272,6 +272,6 @@ impl NVIC {
     where
         I: InterruptNumber,
     {
-        (usize::from(interrupt.number()) % 4) * 8
+        (interrupt.number() % 4) * 8
     }
 }