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[Draft] Multi-Group Scaling for CachePool #17

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[Draft] Multi-Group Scaling for CachePool #17

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65f7337
[SRC] Move the refill xbar into the group level for future scaling.
DiyouS Apr 15, 2026
8cfb9d3
[SRC] Move BootROM inside group level for easier scaling.
DiyouS Apr 16, 2026
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Binary file modified hardware/bootrom/bootrom.elf
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420 changes: 33 additions & 387 deletions hardware/src/cachepool_cluster.sv
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416 changes: 393 additions & 23 deletions hardware/src/cachepool_group.sv
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17 changes: 14 additions & 3 deletions hardware/src/cachepool_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -192,6 +192,13 @@
// UART ID width, with an extra xbar
localparam int unsigned SpatzAxiUartIdWidth = SpatzAxiNarrowIdWidth + $clog2(NumTiles);

// BootROM AXI ID width: wide data bus, muxed from NumTiles tile ports.
// The group's axi_mst_cache slave ID width = GroupAxiIdWidth + 1
// (cluster passes WideIdWidthIn = SpatzAxiIdOutWidth - clog2(NumClusterMst)
// = ClusterAxiIdWidth + 1 - ClusterRouteIdWidth = GroupAxiIdWidth + 1).
// The mux master adds $clog2(NumTiles) bits on top.
localparam int unsigned BootRomAxiSlvIdWidth = GroupAxiIdWidth + 1 + $clog2(NumTiles);

/***** Tile Ports *****/
// We have three sets of AXI ports for each tile:
// 1) Wide output bus for BootRom & L2 (from ICache)
Expand Down Expand Up @@ -286,6 +293,8 @@

typedef logic [IwcAxiIdOutWidth-1:0] axi_id_out_iwc_t;

typedef logic [BootRomAxiSlvIdWidth-1:0] axi_bootrom_slv_id_t;

//////////////////
// TILE TYPES //
//////////////////
Expand Down Expand Up @@ -424,9 +433,11 @@
`AXI_TYPEDEF_ALL(spatz_axi_out, axi_addr_t, axi_id_out_t, axi_wide_data_t, axi_wide_strb_t, axi_user_t)
`AXI_TYPEDEF_ALL(spatz_axi_iwc_out, axi_addr_t, axi_id_out_iwc_t, axi_wide_data_t, axi_wide_strb_t, axi_user_t)

`AXI_TYPEDEF_ALL(axi_uart, axi_addr_t, axi_uart_id_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t)
`AXI_TYPEDEF_ALL(axi_csr_mst, axi_addr_t, axi_id_csr_mst_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t)
`AXI_TYPEDEF_ALL(axi_csr_slv, axi_addr_t, axi_id_csr_slv_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t)
`AXI_TYPEDEF_ALL(axi_uart, axi_addr_t, axi_uart_id_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t)

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[verible-verilog-lint] hardware/src/cachepool_pkg.sv#L436 

Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]" location:{path:"hardware/src/cachepool_pkg.sv" range:{start:{line:436 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
`AXI_TYPEDEF_ALL(axi_csr_mst, axi_addr_t, axi_id_csr_mst_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t)

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[verible-verilog-lint] hardware/src/cachepool_pkg.sv#L437 

Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]" location:{path:"hardware/src/cachepool_pkg.sv" range:{start:{line:437 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
`AXI_TYPEDEF_ALL(axi_csr_slv, axi_addr_t, axi_id_csr_slv_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t)

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[verible-verilog-lint] hardware/src/cachepool_pkg.sv#L438 

Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]" location:{path:"hardware/src/cachepool_pkg.sv" range:{start:{line:438 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
// BootROM: wide data bus (same payload as cache), slv = post-mux (widened ID)
`AXI_TYPEDEF_ALL(axi_bootrom_slv, axi_addr_t, axi_bootrom_slv_id_t, axi_wide_data_t, axi_wide_strb_t, axi_user_t)

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[verible-verilog-lint] hardware/src/cachepool_pkg.sv#L440 

Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]" location:{path:"hardware/src/cachepool_pkg.sv" range:{start:{line:440 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

/**************************************************************
* FUNCTIONS
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4 changes: 0 additions & 4 deletions sim/scripts/vsim_cluster.tcl
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Expand Up @@ -7,10 +7,6 @@ onerror {resume}

set cluster_path $1

add wave -noupdate -group Cluster -group xbar -group req_xbar ${cluster_path}/i_cluster_xbar/i_req_xbar/*
add wave -noupdate -group Cluster -group xbar -group rsp_xbar ${cluster_path}/i_cluster_xbar/i_rsp_xbar/*
add wave -noupdate -group Cluster -group xbar ${cluster_path}/i_cluster_xbar/*

add wave -noupdate -group Cluster -group CSR ${cluster_path}/i_cachepool_cluster_peripheral/*

add wave -noupdate -group Cluster -group Internal ${cluster_path}/*
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4 changes: 4 additions & 0 deletions sim/scripts/vsim_group.tcl
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Expand Up @@ -16,4 +16,8 @@ for {set p 0} {$p < $2} {incr p} {
add wave -noupdate -group Group -group remote_xbar[$p] ${xbar_path}/*
}

add wave -noupdate -group Group -group refill_xbar -group req_xbar ${group_path}/i_refill_xbar/i_req_xbar/*
add wave -noupdate -group Group -group refill_xbar -group rsp_xbar ${group_path}/i_refill_xbar/i_rsp_xbar/*


add wave -noupdate -group Group -group Internal ${group_path}/*
2 changes: 1 addition & 1 deletion util/auto-benchmark/write_results.py
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Expand Up @@ -18,7 +18,7 @@ def extract_uart_lines(input_file_path, output_file_path, config=None, kernel=No

# Copy only lines containing '[UART]'
for line in input_file:
if '[UART]' in line:
if '[UART]' in line or '[EOC]' in line:
output_file.write(line)

output_file.write("\n----------------------------------------\n")
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