GitHub - pooyaaf/Computer-Architecture-Lab: Computer Architecture Lab Projects

Computer Architecture Lab Projects

This repository contains all of my Computer Architecture Lab projects. (Fall 2023)

Collaborators:

Name		Name	Last commit message	Last commit date
Latest commit History 15 Commits
Description		Description
Report		Report
Test		Test
work		work
ALU.v		ALU.v
ARM.cr.mti		ARM.cr.mti
ARM.mpf		ARM.mpf
ARM.v		ARM.v
Adder.v		Adder.v
InstructionMemory.v		InstructionMemory.v
MUX2to1.v		MUX2to1.v
MUX4to1.v		MUX4to1.v
README.md		README.md
RegExecMem.v		RegExecMem.v
RegIDEX.v		RegIDEX.v
RegIFID.v		RegIFID.v
RegMemWB.v		RegMemWB.v
Register.v		Register.v
StageExec.v		StageExec.v
StageID.v		StageID.v
StageIF.v		StageIF.v
StageMem.v		StageMem.v
StageWriteBack.v		StageWriteBack.v
TB.v		TB.v
TB.v.bak		TB.v.bak
Top.v		Top.v
Top.zip		Top.zip
a.out		a.out
cache_controller.v		cache_controller.v
condition_check.v		condition_check.v
control_unit.v		control_unit.v
data_memory.v		data_memory.v
forwarding_unit.v		forwarding_unit.v
hazard_unit.v		hazard_unit.v
register_file.v		register_file.v
sram.v		sram.v
sram_controller.v		sram_controller.v
transcript		transcript
val2_generator.v		val2_generator.v
vsim.wlf		vsim.wlf