Add i440BX Host-PCI Bridge support to chipset resources

[moor-coding]

• Add I440BxHostPciBridgeDeviceHandle with AdjustGpaRangeHandleKind platform resource and I440BX_HOST_PCI_BRIDGE_BDF constant.
• Add I440BxHostPciBridgeResolver async resolver, registered in both openvmm_resources and openvmm_hcl_resources.
• Remove I440BxHostPciBridgeDeps from BaseChipsetDevices and direct construction wiring in base_chipset.rs.
• Add with_i440bx_host_pci_bridge to VmChipsetCapabilities; DSDT generation now reads capabilities instead of the manifest field.

[Copilot]

Pull request overview

This PR moves the i440BX Host-PCI Bridge from direct BaseChipsetBuilder wiring into the resource-resolution system, introducing a platform resource (AdjustGpaRangeHandleKind) and using VmChipsetCapabilities (instead of a manifest field) to drive downstream behavior like DSDT generation.

Changes:

• Add chipset_resources::i440bx_host_pci_bridge resource types (device handle + platform AdjustGpaRange resource + fixed BDF constant).
• Add I440BxHostPciBridgeResolver (async) and register it in both OpenVMM and OpenHCL resource registries.
• Remove I440BxHostPciBridgeDeps from BaseChipsetDevices; switch DSDT generation and IRQ selection logic to use VmChipsetCapabilities::with_i440bx_host_pci_bridge.

Reviewed changes

Copilot reviewed 15 out of 16 changed files in this pull request and generated 1 comment.

Show a summary per file

File	Description
vmm_core/vmotherboard/src/base_chipset.rs	Removes direct i440bx host-bridge dependency wiring; adds VmChipsetCapabilities.with_i440bx_host_pci_bridge.
vmm_core/vm_manifest_builder/src/lib.rs	Attaches i440bx host-bridge via LegacyPciChipsetDeviceHandle and sets the capability bit for Gen1.
vm/devices/chipset_resources/src/lib.rs	Introduces i440bx host-bridge resource definitions, including AdjustGpaRangeHandleKind and fixed BDF.
vm/devices/chipset_resources/Cargo.toml	Adds memory_range dependency required by the new resource trait.
vm/devices/chipset_legacy/src/i440bx_host_pci_bridge/mod.rs	Re-exports AdjustGpaRange/GpaState from chipset_resources and exposes the new resolver module.
vm/devices/chipset_legacy/src/i440bx_host_pci_bridge/resolver.rs	New async resolver constructing HostPciBridge after resolving platform AdjustGpaRange.
vm/devices/chipset_legacy/Cargo.toml	Adds async-trait for the new async resolver implementation.
openvmm/openvmm_resources/src/lib.rs	Registers the i440bx host-bridge resolver for x86_64 guests.
openvmm/openvmm_core/src/worker/dispatch.rs	Removes old deps wiring; uses capabilities for legacy IRQ/DSDT decisions; passes capabilities into DSDT generation.
openvmm/openvmm_core/src/emuplat/i440bx_host_pci_bridge.rs	Adds OpenVMM platform resolver for AdjustGpaRangeHandleKind.
openvmm/openvmm_core/Cargo.toml	Adds parking_lot for the new OpenVMM platform resolver.
openhcl/underhill_core/src/worker.rs	Removes old deps wiring; adds platform resolver registration when capability is enabled.
openhcl/underhill_core/src/emuplat/i440bx_host_pci_bridge.rs	Adds Underhill platform resolver for AdjustGpaRangeHandleKind.
openhcl/underhill_core/Cargo.toml	Adds chipset_resources dependency needed for the platform resolver types.
openhcl/openvmm_hcl_resources/src/lib.rs	Registers the i440bx host-bridge resolver for x86_64 guests.
Cargo.lock	Updates lockfile for newly added dependencies.

[Copilot]

Pull request overview

Copilot reviewed 14 out of 15 changed files in this pull request and generated 1 comment.

[Copilot]

set_ram_visibility(..) returns an error if the requested MemoryRange does not exactly match a controllable RAM region; using .unwrap() here can panic on guest-triggered PAM writes if the memory layout is misconfigured (or if future layouts don’t split RAM into the legacy ranges). Please handle the Err(InvalidRamRegion(..)) path without panicking (e.g., log a rate-limited error/warn and ignore the write, or make the trait return a Result so callers can propagate failures).

Suggested change

	block_on(self.memory.set_ram_visibility(range, state)).unwrap();
	if let Err(err) = block_on(self.memory.set_ram_visibility(range, state)) {
	tracelimit::warn_ratelimited!(
	?range,
	?state,
	error = &err,
	"ignoring PAM RAM visibility update for uncontrollable GPA range"
	);
	}