aes-256

Hardware implementation of AES-256 with Verilog hardware desription language

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
add_round_key.v		add_round_key.v
aes_256_top.v		aes_256_top.v
aes_round_logic.v		aes_round_logic.v
key_expand_256.v		key_expand_256.v
mix_column_128bit.v		mix_column_128bit.v
mix_column_32bit.v		mix_column_32bit.v
rcon_gen.v		rcon_gen.v
rot_word.v		rot_word.v
sbox_128bit.v		sbox_128bit.v
sbox_8bit.v		sbox_8bit.v
shift_row.v		shift_row.v
sub_word.v		sub_word.v

Provide feedback