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refactor(aarch64): Use aarch64-cpu for register access and some memory barriers#598

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Gelbpunkt:aarch64-entry-refactor
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refactor(aarch64): Use aarch64-cpu for register access and some memory barriers#598
Gelbpunkt wants to merge 1 commit intohermit-os:mainfrom
Gelbpunkt:aarch64-entry-refactor

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@Gelbpunkt Gelbpunkt commented Apr 21, 2026

Definitions for DAIFSet were added recently, but are not yet in a release, so the inline assembly that accesses it directly is marked with a FIXME comment.

There are three differences I noticed while going through this:

  • In the TCR setup, the bfi instruction was redundant since it was inserting the same 3 bits that were already shifted to the same position there earlier
  • In TCR_EL1, 0 << 30 was being used to configure 4KiB granule size, which is incorrect. This is not even a valid value for TG1 (bits 30-31). 0x10 is the correct value for 4KiB (the 0x01 for 16KiB was correct but unused)
  • After enabling the MMU, the code performed a branch to flush the pipeline, which we can do more cleanly by inserting an instruction synchronization barrier

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Regarding the missing 56-bit physical address range, I'll open a PR upstream to add it.

@Gelbpunkt Gelbpunkt force-pushed the aarch64-entry-refactor branch from a34ea3f to 75bb927 Compare April 22, 2026 19:53
@Gelbpunkt Gelbpunkt changed the title refactor(aarch64/entry): Use aarch64-cpu for register access and some memory barriers refactor(aarch64): Use aarch64-cpu for register access and some memory barriers Apr 22, 2026
@Gelbpunkt Gelbpunkt force-pushed the aarch64-entry-refactor branch 2 times, most recently from 995e1da to f507c5a Compare April 22, 2026 21:48
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@mkroening mkroening left a comment

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Thanks! :)

Comment thread src/arch/aarch64/entry.rs
Comment thread src/arch/aarch64/mod.rs Outdated
Comment thread src/arch/aarch64/entry.rs Outdated
@Gelbpunkt Gelbpunkt force-pushed the aarch64-entry-refactor branch from f507c5a to 72fd55b Compare April 23, 2026 12:52
…y barriers

Definitions for DAIFSet were added recently, but are not yet in a
release, so the inline assembly that accesses it directly is marked with
a FIXME comment.

There are three differences I noticed while going through this:
- In the TCR setup, the `bfi` instruction was redundant since it was
  inserting the same 3 bits that were already shifted to the same
  position there earlier
- In TCR_EL1, 0 << 30 was being used to configure 4KiB granule size,
  which is incorrect. This is not even a valid value for TG1 (bits
  30-31). 0x10 is the correct value for 4KiB (the 0x01 for 16KiB was
  correct but unused)
- After enabling the MMU, the code performed a branch to flush the
  pipeline, which we can do more cleanly by inserting an instruction
  synchronization barrier
@Gelbpunkt Gelbpunkt force-pushed the aarch64-entry-refactor branch from 72fd55b to bd7c6f9 Compare April 23, 2026 12:54
@Gelbpunkt Gelbpunkt requested a review from mkroening April 23, 2026 12:58
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2 participants