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Fixed race condition and message loss in Cortex-M GNU ports #523

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Fixed race condition and message loss in Cortex-M GNU ports #523

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c05ba69
Fix race condition and message loss in Cortex-M GNU ports (#516)
fdesbiens Apr 13, 2026
6c45adf
Fix race condition and message loss in Cortex-M AC6 ports (#516)
fdesbiens Apr 13, 2026
5819e64
Fix race condition and message loss in Cortex-M IAR ports (#516)
fdesbiens Apr 13, 2026
5b3ac32
Fix race condition and message loss in additional Cortex-M AC6 ports …
fdesbiens Apr 14, 2026
5a845a0
Fix race condition and message loss in all remaining Cortex-M IAR por…
fdesbiens Apr 14, 2026
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3 changes: 3 additions & 0 deletions ports/cortex_m0/gnu/inc/tx_port.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).


/**************************************************************************/
/**************************************************************************/
Expand Down Expand Up @@ -322,6 +324,7 @@ unsigned int interrupt_save;

/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_primask_value();
Expand Down
15 changes: 10 additions & 5 deletions ports/cortex_m0/gnu/src/tx_thread_system_return.S
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Expand Up @@ -5,11 +5,14 @@
@ * terms of the MIT License which is available at
@ * https://opensource.org/licenses/MIT.
@ *
@ * SPDX-License-Identifier: MIT
@ **************************************************************************/
@
@
@/**************************************************************************/
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).


/**************************************************************************/

@/**************************************************************************/
@/** */
@/** ThreadX Component */
Expand Down Expand Up @@ -72,6 +75,8 @@ _tx_thread_system_return:
LDR r0, =0x10000000 @ Load PENDSVSET bit
LDR r1, =0xE000ED04 @ Load NVIC base
STR r0, [r1] @ Set PENDSVBIT in ICSR
DSB #0xF @ Ensure memory access is complete
ISB #0xF @ Flush pipeline
MRS r0, IPSR @ Pickup IPSR
CMP r0, #0 @ Is it a thread returning?
BNE _isr_context @ If ISR, skip interrupt enable
Expand Down
1 change: 1 addition & 0 deletions ports/cortex_m0/iar/inc/tx_port.h
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Original file line number Diff line number Diff line change
Expand Up @@ -313,6 +313,7 @@ __istate_t interrupt_save;

/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_IPSR() == 0)
{
interrupt_save = __get_interrupt_state();
Expand Down
7 changes: 6 additions & 1 deletion ports/cortex_m0/iar/src/tx_thread_system_return.s
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Original file line number Diff line number Diff line change
@@ -1,12 +1,15 @@
;/***************************************************************************
;***************************************************************************
; * Copyright (c) 2024 Microsoft Corporation
; * Copyright (c) 2026-present Eclipse ThreadX contributors
; *
; * This program and the accompanying materials are made available under the
; * terms of the MIT License which is available at
; * https://opensource.org/licenses/MIT.
; *
; * SPDX-License-Identifier: MIT
; **************************************************************************/

; Some portions generated by Gemini (Gemini 2.0 Flash).
;
;
;/**************************************************************************/
Expand Down Expand Up @@ -68,6 +71,8 @@ _tx_thread_system_return:
LDR r0, =0x10000000 ; Load PENDSVSET bit
LDR r1, =0xE000ED04 ; Load NVIC base
STR r0, [r1] ; Set PENDSVBIT in ICSR
DSB SY ; Ensure memory access is complete
ISB SY ; Flush pipeline
MRS r0, IPSR ; Pickup IPSR
CMP r0, #0 ; Is it a thread returning?
BNE _isr_context ; If ISR, skip interrupt enable
Expand Down
3 changes: 3 additions & 0 deletions ports/cortex_m23/ac6/inc/tx_port.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).


/**************************************************************************/
/**************************************************************************/
Expand Down Expand Up @@ -376,6 +378,7 @@ unsigned int was_masked;

/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (_get_ipsr() == 0)
{
was_masked = __disable_irq();
Expand Down
4 changes: 4 additions & 0 deletions ports/cortex_m23/ac6/src/tx_thread_system_return.S
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).


/**************************************************************************/
/**************************************************************************/
Expand Down Expand Up @@ -74,6 +76,8 @@ _tx_thread_system_return:
LDR r0, =0x10000000 // Load PENDSVSET bit
LDR r1, =0xE000ED04 // Load ICSR address
STR r0, [r1] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
Expand Down
3 changes: 3 additions & 0 deletions ports/cortex_m23/gnu/inc/tx_port.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).


/**************************************************************************/
/**************************************************************************/
Expand Down Expand Up @@ -389,6 +391,7 @@ unsigned int interrupt_save;

/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (_get_ipsr() == 0)
{
interrupt_save = __get_primask_value();
Expand Down
4 changes: 4 additions & 0 deletions ports/cortex_m23/gnu/src/tx_thread_system_return.S
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).


/**************************************************************************/
/**************************************************************************/
Expand Down Expand Up @@ -74,6 +76,8 @@ _tx_thread_system_return:
LDR r0, =0x10000000 // Load PENDSVSET bit
LDR r1, =0xE000ED04 // Load ICSR address
STR r0, [r1] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
Expand Down
1 change: 1 addition & 0 deletions ports/cortex_m23/iar/inc/tx_port.h
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Original file line number Diff line number Diff line change
Expand Up @@ -399,6 +399,7 @@ __istate_t interrupt_save;

/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_IPSR() == 0)
{
interrupt_save = __get_interrupt_state();
Expand Down
27 changes: 16 additions & 11 deletions ports/cortex_m23/iar/src/tx_thread_system_return.s
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Original file line number Diff line number Diff line change
@@ -1,16 +1,19 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
;***************************************************************************
;* Copyright (c) 2024 Microsoft Corporation
;* Copyright (c) 2026-present Eclipse ThreadX contributors
;*
;* This program and the accompanying materials are made available under the
;* terms of the MIT License which is available at
;* https://opensource.org/licenses/MIT.
;*
;* SPDX-License-Identifier: MIT
;**************************************************************************

; Some portions generated by Gemini (Gemini 2.0 Flash).


;**************************************************************************

/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
Expand Down Expand Up @@ -65,6 +68,8 @@ _tx_thread_system_return:
LDR r0, =0x10000000 // Load PENDSVSET bit
LDR r1, =0xE000ED04 // Load ICSR address
STR r0, [r1] // Set PENDSVBIT in ICSR
DSB SY // Ensure memory access is complete
ISB SY // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
Expand Down
12 changes: 7 additions & 5 deletions ports/cortex_m3/ac6/inc/tx_port.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).


/**************************************************************************/
/**************************************************************************/
Expand Down Expand Up @@ -539,20 +541,20 @@ unsigned int posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
#endif

__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
}
#endif

__attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int int_posture)
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
//__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory");
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
Expand All @@ -578,6 +580,7 @@ unsigned int interrupt_save;

/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_interrupt_posture();
Expand All @@ -589,7 +592,6 @@ unsigned int interrupt_save;
__restore_interrupt(interrupt_save);
}
}

#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
#define TX_DISABLE interrupt_save = __disable_interrupts();
#define TX_RESTORE __restore_interrupt(interrupt_save);
Expand Down
4 changes: 4 additions & 0 deletions ports/cortex_m3/ac6/src/tx_thread_system_return.S
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).


/**************************************************************************/
/**************************************************************************/
Expand Down Expand Up @@ -73,6 +75,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
Expand Down
6 changes: 4 additions & 2 deletions ports/cortex_m3/gnu/inc/tx_port.h
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).


/**************************************************************************/
/**************************************************************************/
Expand Down Expand Up @@ -539,7 +541,7 @@ unsigned int posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
Expand All @@ -552,7 +554,6 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
//__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
Expand All @@ -578,6 +579,7 @@ unsigned int interrupt_save;

/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_interrupt_posture();
Expand Down
4 changes: 4 additions & 0 deletions ports/cortex_m3/gnu/src/tx_thread_system_return.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).


/**************************************************************************/
/**************************************************************************/
Expand Down Expand Up @@ -73,6 +75,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
Expand Down
12 changes: 7 additions & 5 deletions ports/cortex_m3/iar/inc/tx_port.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).


/**************************************************************************/
/**************************************************************************/
Expand Down Expand Up @@ -539,20 +541,20 @@ unsigned int posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
#endif

__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
}
#endif

__attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int int_posture)
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
//__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory");
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
Expand All @@ -578,6 +580,7 @@ unsigned int interrupt_save;

/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_interrupt_posture();
Expand All @@ -589,7 +592,6 @@ unsigned int interrupt_save;
__restore_interrupt(interrupt_save);
}
}

#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
#define TX_DISABLE interrupt_save = __disable_interrupts();
#define TX_RESTORE __restore_interrupt(interrupt_save);
Expand Down
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