A simple AXI4 DMA unit with an AXI4-Lite register interface written in SpinalHDL.
Simple testbench is included. It also contains a nice AXI4 Bus Memory model.
- 0x00 - source address
- 0x04 - word count - 1
- 0x08 - destination address and trigger
| Name | Name | Last commit date | ||
|---|---|---|---|---|