An open IP forge for open PDKs. ipforge provides production-ready, silicon-proven hardware IP blocks with full physical implementation, sign-off results, and a registry for distribution and reuse.
Each IP is built with open-source EDA tooling, verified with DRC and LVS, and packaged with GDS, LEF, Liberty, CDL, and blackbox stubs for SpinalHDL, Chisel, Verilog, and VHDL.
- IHP SG13G2 — 130 nm BiCMOS
- GlobalFoundries GF180MCU — 180 nm MCU
- SkyWater SKY130 — 130 nm
- gpio — General-purpose I/O controller with APB3 and Wishbone interfaces, configurable direction, input synchronisation, and interrupt controller.
sources/ Hardware IP sources (RTL, constraints, flow configs, tests)
ipforge/ Consumer tool — discover and install IPs (published to PyPI)
ipfab/ Maintainer tool — package, archive, and publish IPs
server/ Cloudflare Workers registry server
export/ SpinalHDL export scripts
Install the consumer tool:
pip install ipforge
Initialise a project and fetch an IP:
ipforge init https://ipforge-registry.aesc-silicon.io --pdk ihp-sg13g2 ipforge remote list ipforge remote fetch aesc-silicon/digital.peripherals.io/gpio
See ipforge/README.rst for full consumer documentation and
ipfab/README.rst for maintainer documentation.
Physical implementation uses OpenROAD Flow Scripts (ORFS) and LibreLane. Sign-off DRC and LVS run via KLayout using PDK-provided rule decks. Simulation uses cocotb with Verilator.
To contribute a new IP or PDK port, fork this repository and follow the
directory structure under sources/. IP-specific documentation lives in
sources/<pdk>/<library>/<name>/doc/.
Hardware sources: CERN-OHL-W-2.0
Software drivers: Apache-2.0