define and prove bit slice operatror v[hi,lo]#27
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xiangze wants to merge 1 commit intoVerilean:mainfrom
Open
define and prove bit slice operatror v[hi,lo]#27xiangze wants to merge 1 commit intoVerilean:mainfrom
xiangze wants to merge 1 commit intoVerilean:mainfrom
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defining signal[a,b] as signal[a:b] in verilog.
because : conflicts lean's operator.