Hardware development branch#12
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RADEFT symbols are in a kicad_sym library file. RADEFT footprints are in a .pretty folder file.
pls work
in process of implementing changes for rev2
uploaded cygnet devboard v1 firmware reference & updated schematic and layout for v2 demo. to do: assign new jlc part numbers
Uses CD-PA1616D from Adafruit
Using RP2350. To do list listed inside KiCAD main page. Will continue to work on it in available time.
- more decoupling caps - i2c address config
-implemented 3.3v to 12v boost converter -radfet readout circuitry done (i think) -added readout circuitry from oresat & proves fc v5c board -finished gps schematic (need footprint still) -added few LEDs main priorities: -watchdog circuit -calculate voltage div resistor values for 12v -gps footprint
- removed pullup resistors on i2c 0 (proves board has the pullups)
- will be adding nand flash for more long term storage of gps and radfet data & telemetry - gps footprint not finished but started. will finish when i get access to a mouse
- refined gps footprint - reorganized schematic
jfets no more for now. Also added footprints to some symbols.
- using analog switch ic to switch between sense & readout (tmux1133) - added non inverting buffer for voltage readout - haven't fully deep dived into the new components & must look into more
-replaced custom circuitry with radfet readout modules -cleaned up sensor schematic page -changed temp sensor -added more missing footprints
layout yay
- circuit layout blocks for ltc3115-1 boost converter, usb LDOs, ethernet 1v and 2.5v completed - rearranged battery holder, moved memory ics, plan to change board dimensions - in progress: layout for power monitor, microsd, peripheral controls, watchdog - grouping components - microsd,
ethernet power tag also fixed in previous commit
- finished microSD layout, payload connector, and some other peripheral layouts but it got messed up when grouping & i didnt notice so yay (i wasted my time) - 3.3v buck completed -replaced satnogs connector footprint -resized board
- finished 5v regulator layout - modified edge cuts to be more refined - new board dimensions (167.67mm x 85.00 mm); shrunk dimensions to make it easier for structures, let me know if you guys think it is unfeasible with new dimensions - satnogs connectors spacing to do: - peripherals - rs 422 connection - canbus connection to satnogs -power monitors -microsd again yay - add general board mounting holes & satnogs mounting holes
watchdog unfinished but in progress
- began placement of some circuit module blocks - another power monitor (satnogs block completed - rearranged usb, ethernet connectors a little to do: - verify buck regulator connections can handle high current - ftdi layout - can bus layout (impedance? need to look into more) - rs-422 layout (need to look into more as well - debug connectors
Has 16 pin smd and 4 through holes
- finished rs-422 payload connector layout (changed footprint, package being used has around 40 left in stock at JLCPCB) - modified memory (mram & nor flash) ic layouts & organized into layout blocks for easy placement later - revised & reorganized gps, rtc, temp sensor, imu connections into separate layout blocks. also moved around gps and moved peripherals into completed layout circuit block section for later placement - changed some power monitor shunt resistor footprints so 10W or so doesnt go thru a sad 0402 resistor lol - fixed microSD connection issues - adjusted gps 50 ohm coax impedance connection (28 ohm trace + 22ohm resistor) - 50 ohm impedance calculations for gps added to schematic & disclaimer for switching regulator low ripple burst mode added to power schematic page to do: - verify that board power monitor wont lead to reverse current driving i.mx8x and make it explode - look further into & verify that cmos image sensor connector is correct one being used by lucid
started placing components onto board itself -satnogs power monitor and connector reoriented -m3 mounting holes will be added to corners - nor flash, mrams added under the som on top layer
- finalized mounting hole place - ftdi layout block complete - more ethernet layout - connections on board
- removed vbus regulators (left vbus unconnected for now, will reconnect to vbus on som later) - outbound signal connectors to adcs & ebyte placement with i2c buffers and power monitors, etc - layout block placement and some connections
mram & nor flash
- payload rs-422 completed - fixed some power net names - can bus to satnogs - gps uart - ftdi uart - spi & octal spi to memories - microsd - more digital signal connections
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phyCORE-i.MX 8X Carrier Board — Revision 1.0 Schematics (03-22-2026)
Summary
This pull request introduces the Revision 1.0 (2026-03-22) schematics for the CADENCE phyCORE-i.MX 8X Carrier Board.
The design provides a platform for the i.MX 8X System on Module (SOM) for use in CADENCE as a flight computer.
Key Features
Schematic Page Overview
Page 1 — Block Diagram
Page 2 — IMX8X SOM Samtec Connectors and Notes
Page 3 — Power System
Power distribution tree implementation:
Page 4 — External Watchdog Timer
Page 5 — User Controls
Page 6 — microSD Interface
Page 7 — Flash and MRAM Memory
Page 8 — Ethernet PHY
Page 9 — Ethernet Connectors
Page 10 — USB Ports
Page 11 — Payload Board Connection
External payload interface:
Page 12 — Blank
Page 13 — GPS and Power Monitor
Page 14 — Onboard Sensors
Sensor/peripheral suite includes:
Page 15 — Debug USB (UART/JTAG)
Page 16 — External and SATNOGS Connections
Interfaces for:
Notes