diff --git a/hardware/bootrom/bootrom.elf b/hardware/bootrom/bootrom.elf index 8c26b6e..6b95750 100755 Binary files a/hardware/bootrom/bootrom.elf and b/hardware/bootrom/bootrom.elf differ diff --git a/hardware/src/cachepool_cluster.sv b/hardware/src/cachepool_cluster.sv index df687a3..e09e599 100644 --- a/hardware/src/cachepool_cluster.sv +++ b/hardware/src/cachepool_cluster.sv @@ -218,16 +218,10 @@ module cachepool_cluster // Wire Definitions // ---------------- // 1. AXI - axi_mst_cache_req_t [NumTiles-1:0][TileNarrowAxiPorts-1:0] axi_tile_req; - axi_mst_cache_resp_t [NumTiles-1:0][TileNarrowAxiPorts-1:0] axi_tile_rsp; - axi_slv_cache_req_t [ClusterWideOutAxiPorts-1 :0] wide_axi_slv_req; - axi_slv_cache_resp_t [ClusterWideOutAxiPorts-1 :0] wide_axi_slv_rsp; - axi_narrow_req_t [NumTiles-1:0][1:0] axi_out_req; - axi_narrow_resp_t [NumTiles-1:0][1:0] axi_out_resp; - - // 2. BootROM - reg_cache_req_t [NumTiles-1:0] bootrom_reg_req; - reg_cache_rsp_t [NumTiles-1:0] bootrom_reg_rsp; + axi_slv_cache_req_t [ClusterWideOutAxiPorts-1:0] wide_axi_slv_req; + axi_slv_cache_resp_t [ClusterWideOutAxiPorts-1:0] wide_axi_slv_rsp; + axi_narrow_req_t [NumTiles-1:0][1:0] axi_out_req; + axi_narrow_resp_t [NumTiles-1:0][1:0] axi_out_resp; // 3. Peripherals axi_addr_t private_start_addr; @@ -245,125 +239,9 @@ module cachepool_cluster // CachePool Tile // --------------- - cache_trans_req_t [NumL1CacheCtrl-1 :0] cache_refill_req; - cache_trans_rsp_t [NumL1CacheCtrl-1 :0] cache_refill_rsp; - - cache_trans_req_t [NumTiles-1 :0] cache_core_req; - cache_trans_rsp_t [NumTiles-1 :0] cache_core_rsp; - - cache_trans_req_chan_t [NumTiles*NumClusterMst-1 :0] tile_req_chan; - cache_trans_rsp_chan_t [NumTiles*NumClusterMst-1 :0] tile_rsp_chan; - logic [NumTiles*NumClusterMst-1 :0] tile_req_valid, tile_req_ready, tile_rsp_valid, tile_rsp_ready; - - l2_req_t [ClusterWideOutAxiPorts-1 :0] l2_req; - l2_rsp_t [ClusterWideOutAxiPorts-1 :0] l2_rsp; - - cache_trans_req_chan_t [ClusterWideOutAxiPorts-1 :0] l2_req_chan; - cache_trans_rsp_chan_t [ClusterWideOutAxiPorts-1 :0] l2_rsp_chan; - logic [ClusterWideOutAxiPorts-1 :0] l2_req_valid, l2_req_ready , l2_rsp_valid, l2_rsp_ready; - - typedef logic [$clog2(NumClusterMst*NumTiles)-1:0] l2_sel_t; - // one more bit for out-of-range alert - typedef logic [$clog2(ClusterWideOutAxiPorts) :0] tile_sel_err_t; - typedef logic [$clog2(ClusterWideOutAxiPorts)-1:0] tile_sel_t; - - // Which l2 we want to select for each req - tile_sel_err_t [NumTiles*NumClusterMst-1 :0] tile_sel_err; - tile_sel_t [NumTiles*NumClusterMst-1 :0] tile_sel; - // Which tile we selected for each req - l2_sel_t [ClusterWideOutAxiPorts-1 :0] tile_selected; - // which tile we want to select for each rsp - l2_sel_t [ClusterWideOutAxiPorts-1 :0] l2_sel; - // What is the priority for response wiring? - // Here we want to make sure the responses from one burst - // continues until done - // If the rsp is a burst with blen != 0, then we will keep - // the rr same, until got a burst rsp with blen == 0 - tile_sel_t [NumTiles*NumClusterMst-1 :0] l2_rsp_rr; - - logic [NumTiles*NumClusterMst-1 :0] rr_lock_d, rr_lock_q; - tile_sel_t [NumTiles*NumClusterMst-1 :0] l2_prio_d, l2_prio_q; - - - l2_sel_t [ClusterWideOutAxiPorts-1:0] port_id; - - for (genvar i = 0; i < ClusterWideOutAxiPorts; i ++) begin - assign port_id[i] = l2_rsp[i].p.user.tile_id * NumClusterMst + l2_rsp[i].p.user.bank_id; - end - - - if (Burst_Enable) begin : gen_burst_ext_sel - `FF(rr_lock_q, rr_lock_d, 1'b0) - `FF(l2_prio_q, l2_prio_d, 1'b0) - - for (genvar port = 0; port < NumTiles*NumClusterMst; port ++) begin : gen_rsp_rr - tile_sel_t l2_rr; - logic [ClusterWideOutAxiPorts-1:0] arb_valid; - for (genvar i = 0; i < ClusterWideOutAxiPorts; i ++) begin - // Used to check the round-robin selection - assign arb_valid[i] = (port_id[i] == port) & l2_rsp_valid[i]; - end - - always_comb begin - l2_prio_d[port] = l2_prio_q[port]; - rr_lock_d[port] = rr_lock_q[port]; - - // Determine the priority we give - // round-robin or locked to previous value? - if (|arb_valid) begin - if (rr_lock_q[port]) begin - // rr is locked because of burst - l2_prio_d[port] = l2_prio_q[port]; - end else begin - l2_prio_d[port] = l2_rr; - end - end - // assigned to xbar rr_i - l2_rsp_rr[port] = l2_prio_d[port]; - - // Lock judgement - // Should it work on the l2_rsp instead of tile_rsp? - if (tile_rsp_chan[port].user.burst.is_burst & |arb_valid) begin - // We got a burst response - if (tile_rsp_chan[port].user.burst.burst_len == 0) begin - // this is the last transaction within a burt, remove lock - rr_lock_d[port] = 1'b0; - end else begin - // the burst response is not finished yet, lock the rr - rr_lock_d[port] = 1'b1; - end - end - end - - // We use the rr_arb_tree to get the round-robin selection - // No data is needed here, only need the handshaking - rr_arb_tree #( - .NumIn ( ClusterWideOutAxiPorts ), - .DataType ( logic ), - .ExtPrio ( 1'b0 ), - .AxiVldRdy ( 1'b1 ), - .LockIn ( 1'b1 ) - ) i_rr_arb_tree ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .flush_i ( '0 ), - .rr_i ( '0 ), - .req_i ( arb_valid ), - .gnt_o ( /*not used*/ ), - .data_i ( '0 ), - .req_o ( /*not used*/ ), - .gnt_i ( tile_rsp_ready[port] ), - .data_o ( /*not used*/ ), - .idx_o ( l2_rr ) - ); - end - end else begin - assign l2_prio_d = '0; - assign l2_prio_q = '0; - assign rr_lock_d = '0; - assign rr_lock_q = '0; - assign l2_rsp_rr = '0; - end + // l2 reqrsp ports from the group (one per L2 channel) + l2_req_t [ClusterWideOutAxiPorts-1:0] l2_req; + l2_rsp_t [ClusterWideOutAxiPorts-1:0] l2_rsp; if (NumTiles > 1) begin : gen_group cachepool_group #( @@ -419,11 +297,9 @@ module cachepool_cluster .private_start_addr_i ( private_start_addr ), .axi_narrow_req_o ( axi_out_req ), .axi_narrow_rsp_i ( axi_out_resp ), - .axi_wide_req_o ( axi_tile_req ), - .axi_wide_rsp_i ( axi_tile_rsp ), - // Cache Refill Ports - .cache_refill_req_o ( cache_refill_req ), - .cache_refill_rsp_i ( cache_refill_rsp ), + // DRAM refill reqrsp (post-xbar, one per L2 channel) + .l2_req_o ( l2_req ), + .l2_rsp_i ( l2_rsp ), // Peripherals .icache_events_o ( icache_events ), .icache_prefetch_enable_i ( icache_prefetch_enable ), @@ -435,32 +311,10 @@ module cachepool_cluster .l1d_insn_ready_o ( l1d_insn_ready ), .l1d_busy_i ( l1d_busy ) ); - // TODO: 2 axi ports converted lost correct assignments - // 1. tile id? - // 2. mux then convert? - for (genvar t = 0; t < NumTiles; t ++) begin : gen_axi_converter - axi_to_reqrsp #( - .axi_req_t ( axi_mst_cache_req_t ), - .axi_rsp_t ( axi_mst_cache_resp_t ), - .AddrWidth ( AxiAddrWidth ), - .DataWidth ( AxiDataWidth ), - .UserWidth ( $bits(refill_user_t) ), - .IdWidth ( AxiIdWidthIn ), - .BufDepth ( NumSpatzOutstandingLoads ), - .reqrsp_req_t ( cache_trans_req_t ), - .reqrsp_rsp_t ( cache_trans_rsp_t ) - ) i_axi2reqrsp ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .busy_o ( ), - .axi_req_i ( axi_tile_req [t][TileMem] ), - .axi_rsp_o ( axi_tile_rsp [t][TileMem] ), - .reqrsp_req_o ( cache_core_req[t] ), - .reqrsp_rsp_i ( cache_core_rsp[t] ) - ); - end end else begin : gen_tile + // TODO: single-tile path not yet migrated to new refill/bootrom datapath. + // This branch is never elaborated in the current configuration (NumTiles > 1 always). cachepool_tile #( .AxiAddrWidth ( AxiAddrWidth ), .AxiDataWidth ( AxiDataWidth ), @@ -516,7 +370,6 @@ module cachepool_cluster .private_start_addr_i ( private_start_addr ), .axi_out_req_o ( axi_out_req [0] ), .axi_out_resp_i ( axi_out_resp [0] ), - // Remote Ports (not used) .remote_req_o ( ), .remote_req_dst_o ( ), .remote_rsp_i ( '0 ), @@ -524,13 +377,11 @@ module cachepool_cluster .remote_req_i ( '0 ), .remote_rsp_o ( ), .remote_rsp_ready_o ( ), - // Cache Refill Ports - .cache_refill_req_o ( cache_refill_req ), - .cache_refill_rsp_i ( cache_refill_rsp ), - .axi_wide_req_o ( axi_tile_req[0] ), - .axi_wide_rsp_i ( axi_tile_rsp[0] ), - // Peripherals - .icache_events_o ( icache_events ), + .cache_refill_req_o ( ), + .cache_refill_rsp_i ( '0 ), + .axi_wide_req_o ( ), + .axi_wide_rsp_i ( '0 ), + .icache_events_o ( ), .icache_prefetch_enable_i ( icache_prefetch_enable ), .cl_interrupt_i ( cl_interrupt ), .dynamic_offset_i ( dynamic_offset ), @@ -540,175 +391,11 @@ module cachepool_cluster .l1d_insn_ready_o ( l1d_insn_ready ), .l1d_busy_i ( l1d_busy ) ); - - axi_to_reqrsp #( - .axi_req_t ( axi_mst_cache_req_t ), - .axi_rsp_t ( axi_mst_cache_resp_t ), - .AddrWidth ( AxiAddrWidth ), - .DataWidth ( AxiDataWidth ), - .UserWidth ( $bits(refill_user_t) ), - .IdWidth ( AxiIdWidthIn ), - .BufDepth ( NumSpatzOutstandingLoads ), - .reqrsp_req_t ( cache_trans_req_t ), - .reqrsp_rsp_t ( cache_trans_rsp_t ) - ) i_axi2reqrsp ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .busy_o ( ), - .axi_req_i ( axi_tile_req [0][TileMem] ), - .axi_rsp_o ( axi_tile_rsp [0][TileMem] ), - .reqrsp_req_o ( cache_core_req[0] ), - .reqrsp_rsp_i ( cache_core_rsp[0] ) - ); - end - - // Additional one port for iCache connection - localparam int unsigned ReqrspPortsTile = NumL1CtrlTile + 1; - always_comb begin - for (int t = 0; t < NumTiles; t++) begin - for (int p = 0; p < ReqrspPortsTile; p++) begin - automatic int unsigned xbar_idx = t*ReqrspPortsTile + p; - automatic int unsigned refill_idx = t*NumL1CtrlTile + p-1; - - if (p == 0) begin - // connect_icache_path - tile_req_chan [xbar_idx] = cache_core_req [t].q; - // Scrmable address - tile_req_chan [xbar_idx].addr = scrambleAddr(cache_core_req[t].q.addr); - tile_req_valid [xbar_idx] = cache_core_req [t].q_valid; - cache_core_rsp [t].q_ready = tile_req_ready [xbar_idx]; - - cache_core_rsp [t].p = tile_rsp_chan [xbar_idx]; - cache_core_rsp [t].p_valid = tile_rsp_valid [xbar_idx]; - tile_rsp_ready [xbar_idx] = cache_core_req [t].p_ready; - // Tile ID assignment - tile_req_chan [xbar_idx].user.tile_id = t; - end else begin - // connect_refill_path - tile_req_chan [xbar_idx] = cache_refill_req[refill_idx].q; - // Scramble address - tile_req_chan [xbar_idx].addr = scrambleAddr(cache_refill_req[refill_idx].q.addr); - tile_req_valid [xbar_idx] = cache_refill_req[refill_idx].q_valid; - cache_refill_rsp[refill_idx].q_ready = tile_req_ready [xbar_idx]; - - cache_refill_rsp[refill_idx].p = tile_rsp_chan [xbar_idx]; - cache_refill_rsp[refill_idx].p_valid = tile_rsp_valid [xbar_idx]; - tile_rsp_ready [xbar_idx] = cache_refill_req[refill_idx].p_ready; - // Tile ID assignment - tile_req_chan [xbar_idx].user.tile_id = t; - end - end - end - end - - typedef struct packed { - int unsigned idx; - logic [AxiAddrWidth-1:0] base; - logic [AxiAddrWidth-1:0] mask; - } reqrsp_rule_t; - - reqrsp_rule_t [ClusterWideOutAxiPorts-1:0] xbar_rule; - - for (genvar i = 0; i < ClusterWideOutAxiPorts; i ++) begin - assign xbar_rule[i] = '{ - idx : i, - base : DramAddr + DramPerChSize * i, - mask : ({AxiAddrWidth{1'b1}} << $clog2(DramPerChSize)) - }; - end - - logic [$clog2(ClusterWideOutAxiPorts):0] default_idx; - assign default_idx = ClusterWideOutAxiPorts; - - for (genvar inp = 0; inp < NumClusterMst*NumTiles; inp ++) begin : gen_xbar_sel - addr_decode_napot #( - .NoIndices (ClusterWideOutAxiPorts+1 ), - .NoRules (ClusterWideOutAxiPorts ), - .addr_t (axi_addr_t ), - .rule_t (reqrsp_rule_t ) - ) i_snitch_decode_napot ( - .addr_i (tile_req_chan[inp].addr), - .addr_map_i (xbar_rule ), - .idx_o (tile_sel_err[inp] ), - .dec_valid_o (/* Unused */ ), - .dec_error_o (/* Unused */ ), - .en_default_idx_i (1'b1 ), - .default_idx_i (default_idx ) - ); - - assign tile_sel[inp] = tile_sel_err[inp][$clog2(ClusterWideOutAxiPorts)-1:0]; - -`ifndef TARGET_SYNTHESIS - // Alert the system that we have illegal memory access - IllegalMemAccess : assert property( - @(posedge clk_i) disable iff (!rst_ni) (tile_req_valid[inp] |-> !tile_sel_err[inp][$clog2(ClusterWideOutAxiPorts)])) - else $error("Visited illegal address: time=%0t, port=%0d, addr=0x%08h", $time, inp, tile_req_chan[inp].addr); - // else $fatal (1, "Visited address is not mapped"); -`endif - end - - reqrsp_xbar #( - .NumInp (NumClusterMst*NumTiles ), - .NumOut (ClusterWideOutAxiPorts ), - .PipeReg (1'b1 ), - .ExtReqPrio (1'b0 ), - .ExtRspPrio (Burst_Enable ), - .tcdm_req_chan_t (cache_trans_req_chan_t ), - .tcdm_rsp_chan_t (cache_trans_rsp_chan_t ) - ) i_cluster_xbar ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .slv_req_i (tile_req_chan ), - .slv_req_valid_i (tile_req_valid ), - .slv_req_ready_o (tile_req_ready ), - .slv_rsp_o (tile_rsp_chan ), - .slv_rsp_valid_o (tile_rsp_valid ), - .slv_rsp_ready_i (tile_rsp_ready ), - .slv_sel_i (tile_sel[NumTiles*NumClusterMst-1:0] ), - .slv_rr_i ('0 ), - .slv_selected_o (tile_selected ), - .mst_req_o (l2_req_chan ), - .mst_req_valid_o (l2_req_valid ), - .mst_req_ready_i (l2_req_ready ), - .mst_rsp_i (l2_rsp_chan ), - .mst_rr_i (l2_rsp_rr ), - .mst_rsp_valid_i (l2_rsp_valid ), - .mst_rsp_ready_o (l2_rsp_ready ), - .mst_sel_i (l2_sel ) - ); - - for (genvar ch = 0; ch < ClusterWideOutAxiPorts; ch++) begin - // To L2 Channels - always_comb begin - l2_req[ch].q = '{ - addr : l2_req_chan[ch].addr, - write: l2_req_chan[ch].write, - amo : l2_req_chan[ch].amo, - data : l2_req_chan[ch].data, - strb : l2_req_chan[ch].strb, - size : l2_req_chan[ch].size, - default: '0 - }; - l2_req[ch].q.user = l2_req_chan[ch].user; - l2_req[ch].q_valid = l2_req_valid[ch] ; - l2_req_ready[ch] = l2_rsp[ch].q_ready; - - l2_rsp_chan [ch] = '{ - data : l2_rsp[ch].p.data, - error: l2_rsp[ch].p.error, - write: l2_rsp[ch].p.write, - default: '0 - }; - l2_rsp_chan [ch].user = l2_rsp[ch].p.user; - l2_rsp_valid[ch] = l2_rsp[ch].p_valid; - l2_req[ch].p_ready = l2_rsp_ready[ch]; - // calculate the port from the tile id and bank id - // bank_id == 0 --- bypass - // bank_id == 1-4 --- cache bank 0-3 - l2_sel[ch] = l2_rsp[ch].p.user.tile_id * NumClusterMst + l2_rsp[ch].p.user.bank_id; - end end + // ------------- + // To Main Memory: reqrsp_to_axi + output cut, consuming group l2 reqrsp ports + // ------------- for (genvar ch = 0; ch < ClusterWideOutAxiPorts; ch ++) begin : gen_output_axi reqrsp_to_axi #( .MaxTrans (NumSpatzOutstandingLoads*2 ), @@ -723,7 +410,7 @@ module cachepool_cluster .reqrsp_rsp_t (l2_rsp_t ), .axi_req_t (axi_slv_cache_req_t ), .axi_rsp_t (axi_slv_cache_resp_t ) - ) i_reqrsp2axi ( + ) i_reqrsp2axi ( .clk_i (clk_i ), .rst_ni (rst_ni ), .user_i (l2_req[ch].q.user ), @@ -734,10 +421,6 @@ module cachepool_cluster ); end - - // ------------- - // To Main Memory - // ------------- // Optionally decouple the external wide AXI master port. for (genvar port = 0; port < ClusterWideOutAxiPorts; port ++) begin : gen_axi_out_cut axi_cut #( @@ -810,43 +493,6 @@ module cachepool_cluster assign axi_out_resp[0][ClusterUart] = axi_narrow_resp_i; end - /***** BootROM ****/ - for (genvar t = 0; t < NumTiles; t++) begin : gen_bootrom - axi_to_reg #( - .ADDR_WIDTH (AxiAddrWidth ), - .DATA_WIDTH (AxiDataWidth ), - .AXI_MAX_WRITE_TXNS (1 ), - .AXI_MAX_READ_TXNS (1 ), - .DECOUPLE_W (0 ), - .ID_WIDTH (WideIdWidthIn ), - .USER_WIDTH (AxiUserWidth ), - .axi_req_t (axi_mst_cache_req_t ), - .axi_rsp_t (axi_mst_cache_resp_t), - .reg_req_t (reg_cache_req_t ), - .reg_rsp_t (reg_cache_rsp_t ) - ) i_axi_to_reg_bootrom ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .testmode_i (1'b0 ), - .axi_req_i (axi_tile_req[t][TileBootROM] ), - .axi_rsp_o (axi_tile_rsp[t][TileBootROM] ), - .reg_req_o (bootrom_reg_req[t] ), - .reg_rsp_i (bootrom_reg_rsp[t] ) - ); - - bootrom i_bootrom ( - .clk_i (clk_i ), - .req_i (bootrom_reg_req[t].valid ), - .addr_i (addr_t'(bootrom_reg_req[t].addr) ), - .rdata_o(bootrom_reg_rsp[t].rdata ) - ); - - `FF(bootrom_reg_rsp[t].ready, bootrom_reg_req[t].valid, 1'b0) - - assign bootrom_reg_rsp[t].error = 1'b0; - end - - /***** CSR/Peripherals *****/ `REG_BUS_TYPEDEF_ALL(reg, narrow_addr_t, narrow_data_t, narrow_strb_t) @@ -920,13 +566,13 @@ module cachepool_cluster .SpillR ( XbarLatency[0] ), .MaxWTrans ( 2 ) ) i_axi_csr_mux ( - .clk_i ( clk_i ), // Clock - .rst_ni ( rst_ni ), // Asynchronous reset active low - .test_i ('0 ), // Test Mode enable + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_i ('0 ), .slv_reqs_i ( {axi_in_req_i, axi_core_csr_req} ), .slv_resps_o ( {axi_in_resp_o, axi_core_csr_rsp} ), - .mst_req_o ( axi_csr_req ), - .mst_resp_i ( axi_csr_rsp ) + .mst_req_o ( axi_csr_req ), + .mst_resp_i ( axi_csr_rsp ) ); axi_to_reg #( @@ -942,13 +588,13 @@ module cachepool_cluster .reg_req_t (reg_req_t ), .reg_rsp_t (reg_rsp_t ) ) i_csr_axi_to_reg ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .testmode_i (1'b0 ), - .axi_req_i (axi_csr_req ), - .axi_rsp_o (axi_csr_rsp ), - .reg_req_o (reg_req ), - .reg_rsp_i (reg_rsp ) + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .testmode_i (1'b0 ), + .axi_req_i (axi_csr_req ), + .axi_rsp_o (axi_csr_rsp ), + .reg_req_o (reg_req ), + .reg_rsp_i (reg_rsp ) ); diff --git a/hardware/src/cachepool_group.sv b/hardware/src/cachepool_group.sv index 772626f..bce8423 100644 --- a/hardware/src/cachepool_group.sv +++ b/hardware/src/cachepool_group.sv @@ -139,13 +139,10 @@ module cachepool_group /// AXI Narrow out-port (UART/Peripheral) output axi_narrow_req_t [GroupNarrowAxiPorts-1:0] axi_narrow_req_o, input axi_narrow_resp_t [GroupNarrowAxiPorts-1:0] axi_narrow_rsp_i, - /// Wide AXI ports to cluster level - output axi_out_req_t [GroupWideAxiPorts-1:0] axi_wide_req_o, - input axi_out_resp_t [GroupWideAxiPorts-1:0] axi_wide_rsp_i, - /// Cache refill ports - output cache_trans_req_t [NumL1CacheCtrl-1:0] cache_refill_req_o, - input cache_trans_rsp_t [NumL1CacheCtrl-1:0] cache_refill_rsp_i, + /// DRAM refill reqrsp ports (post-xbar, one per L2 channel) + output l2_req_t [ClusterWideOutAxiPorts-1:0] l2_req_o, + input l2_rsp_t [ClusterWideOutAxiPorts-1:0] l2_rsp_i, /// Peripheral signals output icache_events_t [NrCores-1:0] icache_events_o, @@ -153,10 +150,10 @@ module cachepool_group input logic [NrCores-1:0] cl_interrupt_i, input logic [$clog2(AxiAddrWidth)-1:0] dynamic_offset_i, input logic [3:0] l1d_private_i, - input cache_insn_t l1d_insn_i, + input cache_insn_t l1d_insn_i, input logic l1d_insn_valid_i, - output logic [NumTiles-1:0] l1d_insn_ready_o, - input logic [NumTiles-1:0] l1d_busy_i, + output logic [NumTiles-1:0] l1d_insn_ready_o, + input logic [NumTiles-1:0] l1d_busy_i, /// SRAM Configuration input impl_in_t [NrSramCfg-1:0] impl_i, @@ -217,6 +214,380 @@ module cachepool_group logic [NumTiles-1:0] error; assign error_o = |error; + // Internal tile-side wide AXI: split into two flat arrays by port function + // BootROM (TileBootROM=0): muxed into single shared bootrom in this group + axi_mst_cache_req_t [NumTiles-1:0] axi_tile_bootrom_req; + axi_mst_cache_resp_t [NumTiles-1:0] axi_tile_bootrom_rsp; + // TileMem (TileMem=1): stays in group, fed into axi_to_reqrsp + axi_mst_cache_req_t [NumTiles-1:0] axi_tile_mem_req; + axi_mst_cache_resp_t [NumTiles-1:0] axi_tile_mem_rsp; + + // Mux all per-tile BootROM AXI ports into a single bootrom instance + axi_bootrom_slv_req_t axi_bootrom_mux_req; + axi_bootrom_slv_resp_t axi_bootrom_mux_rsp; + + if (NumTiles > 1) begin : gen_bootrom_mux + axi_mux #( + .SlvAxiIDWidth ( WideIdWidthIn ), + .slv_aw_chan_t ( axi_mst_cache_aw_chan_t ), + .mst_aw_chan_t ( axi_bootrom_slv_aw_chan_t ), + .w_chan_t ( axi_mst_cache_w_chan_t ), + .slv_b_chan_t ( axi_mst_cache_b_chan_t ), + .mst_b_chan_t ( axi_bootrom_slv_b_chan_t ), + .slv_ar_chan_t ( axi_mst_cache_ar_chan_t ), + .mst_ar_chan_t ( axi_bootrom_slv_ar_chan_t ), + .slv_r_chan_t ( axi_mst_cache_r_chan_t ), + .mst_r_chan_t ( axi_bootrom_slv_r_chan_t ), + .slv_req_t ( axi_mst_cache_req_t ), + .slv_resp_t ( axi_mst_cache_resp_t ), + .mst_req_t ( axi_bootrom_slv_req_t ), + .mst_resp_t ( axi_bootrom_slv_resp_t ), + .NoSlvPorts ( NumTiles ), + .FallThrough ( 0 ), + .SpillAw ( XbarLatency[4] ), + .SpillW ( XbarLatency[3] ), + .SpillB ( XbarLatency[2] ), + .SpillAr ( XbarLatency[1] ), + .SpillR ( XbarLatency[0] ), + .MaxWTrans ( 2 ) + ) i_axi_bootrom_mux ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_i ( '0 ), + .slv_reqs_i ( axi_tile_bootrom_req ), + .slv_resps_o( axi_tile_bootrom_rsp ), + .mst_req_o ( axi_bootrom_mux_req ), + .mst_resp_i ( axi_bootrom_mux_rsp ) + ); + end else begin : gen_bootrom_connect + // NumTiles==1: direct connect, no ID widening needed + assign axi_bootrom_mux_req = axi_bootrom_slv_req_t'(axi_tile_bootrom_req[0]); + assign axi_tile_bootrom_rsp[0] = axi_mst_cache_resp_t'(axi_bootrom_mux_rsp); + end + + // Single BootROM instance shared across all tiles in the group + `REG_BUS_TYPEDEF_ALL(reg_bootrom, addr_t, data_cache_t, strb_cache_t) + reg_bootrom_req_t bootrom_reg_req; + reg_bootrom_rsp_t bootrom_reg_rsp; + + axi_to_reg #( + .ADDR_WIDTH ( AxiAddrWidth ), + .DATA_WIDTH ( AxiDataWidth ), + .AXI_MAX_WRITE_TXNS ( 1 ), + .AXI_MAX_READ_TXNS ( 1 ), + .DECOUPLE_W ( 0 ), + .ID_WIDTH ( BootRomAxiSlvIdWidth ), + .USER_WIDTH ( AxiUserWidth ), + .axi_req_t ( axi_bootrom_slv_req_t ), + .axi_rsp_t ( axi_bootrom_slv_resp_t ), + .reg_req_t ( reg_bootrom_req_t ), + .reg_rsp_t ( reg_bootrom_rsp_t ) + ) i_axi_to_reg_bootrom ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( 1'b0 ), + .axi_req_i ( axi_bootrom_mux_req ), + .axi_rsp_o ( axi_bootrom_mux_rsp ), + .reg_req_o ( bootrom_reg_req ), + .reg_rsp_i ( bootrom_reg_rsp ) + ); + + bootrom i_bootrom ( + .clk_i ( clk_i ), + .req_i ( bootrom_reg_req.valid ), + .addr_i ( addr_t'(bootrom_reg_req.addr) ), + .rdata_o ( bootrom_reg_rsp.rdata ) + ); + + `FF(bootrom_reg_rsp.ready, bootrom_reg_req.valid, 1'b0) + assign bootrom_reg_rsp.error = 1'b0; + + // Cache refill ports from tiles (NumL1CacheCtrl = NumCores total) + cache_trans_req_t [NumL1CacheCtrl-1:0] cache_refill_req; + cache_trans_rsp_t [NumL1CacheCtrl-1:0] cache_refill_rsp; + + // cache_core_req/rsp: icache-bypass path, one per tile (from axi_to_reqrsp) + cache_trans_req_t [NumTiles-1:0] cache_core_req; + cache_trans_rsp_t [NumTiles-1:0] cache_core_rsp; + + // Flat xbar input channels: NumTiles * NumClusterMst ports + cache_trans_req_chan_t [NumTiles*NumClusterMst-1:0] tile_req_chan; + cache_trans_rsp_chan_t [NumTiles*NumClusterMst-1:0] tile_rsp_chan; + logic [NumTiles*NumClusterMst-1:0] tile_req_valid, tile_req_ready, + tile_rsp_valid, tile_rsp_ready; + + // Xbar output channels: one per L2 channel + cache_trans_req_chan_t [ClusterWideOutAxiPorts-1:0] l2_req_chan; + cache_trans_rsp_chan_t [ClusterWideOutAxiPorts-1:0] l2_rsp_chan; + logic [ClusterWideOutAxiPorts-1:0] l2_req_valid, l2_req_ready, + l2_rsp_valid, l2_rsp_ready; + + // Selection types + typedef logic [$clog2(NumClusterMst*NumTiles)-1:0] l2_sel_t; + typedef logic [$clog2(ClusterWideOutAxiPorts) :0] tile_sel_err_t; // one extra bit for OOB + typedef logic [$clog2(ClusterWideOutAxiPorts)-1:0] tile_sel_t; + + tile_sel_err_t [NumTiles*NumClusterMst-1:0] tile_sel_err; + tile_sel_t [NumTiles*NumClusterMst-1:0] tile_sel; + l2_sel_t [ClusterWideOutAxiPorts-1:0] tile_selected; + l2_sel_t [ClusterWideOutAxiPorts-1:0] l2_sel; + tile_sel_t [NumTiles*NumClusterMst-1:0] l2_rsp_rr; + + logic [NumTiles*NumClusterMst-1:0] rr_lock_d, rr_lock_q; + tile_sel_t [NumTiles*NumClusterMst-1:0] l2_prio_d, l2_prio_q; + + // port_id: which xbar input port does each L2 channel response target + l2_sel_t [ClusterWideOutAxiPorts-1:0] port_id; + for (genvar i = 0; i < ClusterWideOutAxiPorts; i++) begin + assign port_id[i] = l2_rsp_i[i].p.user.tile_id * NumClusterMst + + l2_rsp_i[i].p.user.bank_id; + end + + // --------------------- + // axi_to_reqrsp: TileMem (icache-bypass) path, one per tile + // --------------------- + for (genvar t = 0; t < NumTiles; t++) begin : gen_axi_converter + axi_to_reqrsp #( + .axi_req_t ( axi_mst_cache_req_t ), + .axi_rsp_t ( axi_mst_cache_resp_t ), + .AddrWidth ( AxiAddrWidth ), + .DataWidth ( AxiDataWidth ), + .UserWidth ( $bits(refill_user_t) ), + .IdWidth ( AxiIdWidthIn ), + .BufDepth ( NumSpatzOutstandingLoads ), + .reqrsp_req_t ( cache_trans_req_t ), + .reqrsp_rsp_t ( cache_trans_rsp_t ) + ) i_axi2reqrsp ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .busy_o ( ), + .axi_req_i ( axi_tile_mem_req[t] ), + .axi_rsp_o ( axi_tile_mem_rsp[t] ), + .reqrsp_req_o ( cache_core_req[t] ), + .reqrsp_rsp_i ( cache_core_rsp[t] ) + ); + end + + // --------------------- + // Wiring: assemble flat xbar input from icache-bypass and refill paths + // --------------------- + // Port layout per tile: p=0 -> icache-bypass (cache_core_req), + // p=1..NumL1CtrlTile -> refill (cache_refill_req) + localparam int unsigned ReqrspPortsTile = NumL1CtrlTile + 1; + always_comb begin + for (int t = 0; t < NumTiles; t++) begin + for (int p = 0; p < ReqrspPortsTile; p++) begin + automatic int unsigned xbar_idx = t * ReqrspPortsTile + p; + automatic int unsigned refill_idx = t * NumL1CtrlTile + p - 1; + + if (p == 0) begin + // icache-bypass path + tile_req_chan [xbar_idx] = cache_core_req[t].q; + tile_req_chan [xbar_idx].addr = scrambleAddr(cache_core_req[t].q.addr); + tile_req_valid [xbar_idx] = cache_core_req[t].q_valid; + cache_core_rsp [t].q_ready = tile_req_ready[xbar_idx]; + + cache_core_rsp [t].p = tile_rsp_chan [xbar_idx]; + cache_core_rsp [t].p_valid = tile_rsp_valid[xbar_idx]; + tile_rsp_ready [xbar_idx] = cache_core_req[t].p_ready; + tile_req_chan [xbar_idx].user.tile_id = t; + end else begin + // refill path + tile_req_chan [xbar_idx] = cache_refill_req[refill_idx].q; + tile_req_chan [xbar_idx].addr = scrambleAddr(cache_refill_req[refill_idx].q.addr); + tile_req_valid [xbar_idx] = cache_refill_req[refill_idx].q_valid; + cache_refill_rsp[refill_idx].q_ready = tile_req_ready[xbar_idx]; + + cache_refill_rsp[refill_idx].p = tile_rsp_chan [xbar_idx]; + cache_refill_rsp[refill_idx].p_valid = tile_rsp_valid[xbar_idx]; + tile_rsp_ready [xbar_idx] = cache_refill_req[refill_idx].p_ready; + tile_req_chan [xbar_idx].user.tile_id = t; + end + end + end + end + + // --------------------- + // Address decoder: select L2 channel per xbar input port + // --------------------- + typedef struct packed { + int unsigned idx; + logic [AxiAddrWidth-1:0] base; + logic [AxiAddrWidth-1:0] mask; + } reqrsp_rule_t; + + reqrsp_rule_t [ClusterWideOutAxiPorts-1:0] xbar_rule; + for (genvar i = 0; i < ClusterWideOutAxiPorts; i++) begin + assign xbar_rule[i] = '{ + idx : i, + base : DramAddr + DramPerChSize * i, + mask : ({AxiAddrWidth{1'b1}} << $clog2(DramPerChSize)) + }; + end + + logic [$clog2(ClusterWideOutAxiPorts):0] default_idx; + assign default_idx = ClusterWideOutAxiPorts; + + for (genvar inp = 0; inp < NumClusterMst*NumTiles; inp++) begin : gen_xbar_sel + addr_decode_napot #( + .NoIndices ( ClusterWideOutAxiPorts+1 ), + .NoRules ( ClusterWideOutAxiPorts ), + .addr_t ( axi_addr_t ), + .rule_t ( reqrsp_rule_t ) + ) i_snitch_decode_napot ( + .addr_i ( tile_req_chan[inp].addr ), + .addr_map_i ( xbar_rule ), + .idx_o ( tile_sel_err[inp] ), + .dec_valid_o ( /* unused */ ), + .dec_error_o ( /* unused */ ), + .en_default_idx_i ( 1'b1 ), + .default_idx_i ( default_idx ) + ); + assign tile_sel[inp] = tile_sel_err[inp][$clog2(ClusterWideOutAxiPorts)-1:0]; + +`ifndef TARGET_SYNTHESIS + IllegalMemAccess : assert property ( + @(posedge clk_i) disable iff (!rst_ni) + (tile_req_valid[inp] |-> !tile_sel_err[inp][$clog2(ClusterWideOutAxiPorts)])) + else $error("Visited illegal address: time=%0t, port=%0d, addr=0x%08h", + $time, inp, tile_req_chan[inp].addr); +`endif + end + + // --------------------- + // Burst protection logic + // --------------------- + if (Burst_Enable) begin : gen_burst_ext_sel + `FF(rr_lock_q, rr_lock_d, 1'b0) + `FF(l2_prio_q, l2_prio_d, 1'b0) + + for (genvar port = 0; port < NumTiles*NumClusterMst; port++) begin : gen_rsp_rr + tile_sel_t l2_rr; + logic [ClusterWideOutAxiPorts-1:0] arb_valid; + + for (genvar i = 0; i < ClusterWideOutAxiPorts; i++) begin + assign arb_valid[i] = (port_id[i] == port) & l2_rsp_valid[i]; + end + + always_comb begin + l2_prio_d[port] = l2_prio_q[port]; + rr_lock_d[port] = rr_lock_q[port]; + + if (|arb_valid) begin + if (rr_lock_q[port]) begin + l2_prio_d[port] = l2_prio_q[port]; + end else begin + l2_prio_d[port] = l2_rr; + end + end + l2_rsp_rr[port] = l2_prio_d[port]; + + if (tile_rsp_chan[port].user.burst.is_burst & |arb_valid) begin + if (tile_rsp_chan[port].user.burst.burst_len == 0) begin + rr_lock_d[port] = 1'b0; + end else begin + rr_lock_d[port] = 1'b1; + end + end + end + + rr_arb_tree #( + .NumIn ( ClusterWideOutAxiPorts ), + .DataType ( logic ), + .ExtPrio ( 1'b0 ), + .AxiVldRdy ( 1'b1 ), + .LockIn ( 1'b1 ) + ) i_rr_arb_tree ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( '0 ), + .rr_i ( '0 ), + .req_i ( arb_valid ), + .gnt_o ( /* not used */ ), + .data_i ( '0 ), + .req_o ( /* not used */ ), + .gnt_i ( tile_rsp_ready[port]), + .data_o ( /* not used */ ), + .idx_o ( l2_rr ) + ); + end + end else begin + assign l2_prio_d = '0; + assign l2_prio_q = '0; + assign rr_lock_d = '0; + assign rr_lock_q = '0; + assign l2_rsp_rr = '0; + end + + // --------------------- + // Refill (DRAM) xbar + // --------------------- + reqrsp_xbar #( + .NumInp ( NumClusterMst*NumTiles ), + .NumOut ( ClusterWideOutAxiPorts ), + .PipeReg ( 1'b1 ), + .ExtReqPrio ( 1'b0 ), + .ExtRspPrio ( Burst_Enable ), + .tcdm_req_chan_t ( cache_trans_req_chan_t ), + .tcdm_rsp_chan_t ( cache_trans_rsp_chan_t ) + ) i_refill_xbar ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( tile_req_chan ), + .slv_req_valid_i ( tile_req_valid ), + .slv_req_ready_o ( tile_req_ready ), + .slv_rsp_o ( tile_rsp_chan ), + .slv_rsp_valid_o ( tile_rsp_valid ), + .slv_rsp_ready_i ( tile_rsp_ready ), + .slv_sel_i ( tile_sel[NumTiles*NumClusterMst-1:0] ), + .slv_rr_i ( '0 ), + .slv_selected_o ( tile_selected ), + .mst_req_o ( l2_req_chan ), + .mst_req_valid_o ( l2_req_valid ), + .mst_req_ready_i ( l2_req_ready ), + .mst_rsp_i ( l2_rsp_chan ), + .mst_rr_i ( l2_rsp_rr ), + .mst_rsp_valid_i ( l2_rsp_valid ), + .mst_rsp_ready_o ( l2_rsp_ready ), + .mst_sel_i ( l2_sel ) + ); + + // --------------------- + // l2_req/rsp packing: bridge xbar channels <-> l2_req_t/l2_rsp_t port + // --------------------- + for (genvar ch = 0; ch < ClusterWideOutAxiPorts; ch++) begin : gen_l2_pack + always_comb begin + // Request: xbar -> group output port + l2_req_o[ch].q = '{ + addr : l2_req_chan[ch].addr, + write : l2_req_chan[ch].write, + amo : l2_req_chan[ch].amo, + data : l2_req_chan[ch].data, + strb : l2_req_chan[ch].strb, + size : l2_req_chan[ch].size, + default: '0 + }; + l2_req_o[ch].q.user = l2_req_chan[ch].user; + l2_req_o[ch].q_valid = l2_req_valid[ch]; + l2_req_ready[ch] = l2_rsp_i[ch].q_ready; + + // Response: group input port -> xbar + l2_rsp_chan[ch] = '{ + data : l2_rsp_i[ch].p.data, + error : l2_rsp_i[ch].p.error, + write : l2_rsp_i[ch].p.write, + default: '0 + }; + l2_rsp_chan[ch].user = l2_rsp_i[ch].p.user; + l2_rsp_valid[ch] = l2_rsp_i[ch].p_valid; + l2_req_o[ch].p_ready = l2_rsp_ready[ch]; + + // Response demux: which xbar input port does this response target? + l2_sel[ch] = l2_rsp_i[ch].p.user.tile_id * NumClusterMst + + l2_rsp_i[ch].p.user.bank_id; + end + end + // Tile remote access signals // In/Out relative to the tile (out--leave a tile; in--enter a tile) // Tile-side flat layout: index = j + r*NrTCDMPortsPerCore (j=xbar idx, r=remote slot within xbar) @@ -330,8 +701,7 @@ module cachepool_group .clk_i ( clk_i ), .rst_ni ( rst_ni ), .impl_i ( impl_i ), - .error_o ( error[t] ), - // TODO: remove hardcode + .error_o ( error [t] ), .debug_req_i ( debug_req_i [t*NumCoresTile+:NumCoresTile] ), .meip_i ( meip_i [t*NumCoresTile+:NumCoresTile] ), .mtip_i ( mtip_i [t*NumCoresTile+:NumCoresTile] ), @@ -344,19 +714,19 @@ module cachepool_group .axi_out_req_o ( axi_narrow_req_o [t*TileNarrowAxiPorts+:TileNarrowAxiPorts]), .axi_out_resp_i ( axi_narrow_rsp_i [t*TileNarrowAxiPorts+:TileNarrowAxiPorts]), // Remote Access Ports - .remote_req_o ( tile_remote_out_req[t] ), - .remote_req_dst_o ( remote_out_sel_tile[t] ), - .remote_rsp_i ( tile_remote_out_rsp[t] ), + .remote_req_o ( tile_remote_out_req [t] ), + .remote_req_dst_o ( remote_out_sel_tile [t] ), + .remote_rsp_i ( tile_remote_out_rsp [t] ), .remote_rsp_ready_i ( tile_remote_out_ready[t] ), - .remote_req_i ( tile_remote_in_req [t] ), - .remote_rsp_o ( tile_remote_in_rsp [t] ), - .remote_rsp_ready_o ( tile_remote_in_ready[t] ), - // Cache Refill Ports - .cache_refill_req_o ( cache_refill_req_o[t*NumL1CtrlTile+:NumL1CtrlTile] ), - .cache_refill_rsp_i ( cache_refill_rsp_i[t*NumL1CtrlTile+:NumL1CtrlTile] ), - // BootROM / Core-side Cache Bypass - .axi_wide_req_o ( axi_wide_req_o [t*TileWideAxiPorts+:TileWideAxiPorts] ), - .axi_wide_rsp_i ( axi_wide_rsp_i [t*TileWideAxiPorts+:TileWideAxiPorts] ), + .remote_req_i ( tile_remote_in_req [t] ), + .remote_rsp_o ( tile_remote_in_rsp [t] ), + .remote_rsp_ready_o ( tile_remote_in_ready [t] ), + // Cache Refill Ports (now internal, connected to group-level xbar) + .cache_refill_req_o ( cache_refill_req[t*NumL1CtrlTile+:NumL1CtrlTile] ), + .cache_refill_rsp_i ( cache_refill_rsp[t*NumL1CtrlTile+:NumL1CtrlTile] ), + // BootROM (goes to cluster) / Core-side Cache Bypass (stays in group) + .axi_wide_req_o ( {axi_tile_mem_req[t], axi_tile_bootrom_req[t]} ), + .axi_wide_rsp_i ( {axi_tile_mem_rsp[t], axi_tile_bootrom_rsp[t]} ), // Peripherals .icache_events_o ( /* unused */ ), .icache_prefetch_enable_i ( icache_prefetch_enable_i ), diff --git a/hardware/src/cachepool_pkg.sv b/hardware/src/cachepool_pkg.sv index 737bc70..ef97cfe 100644 --- a/hardware/src/cachepool_pkg.sv +++ b/hardware/src/cachepool_pkg.sv @@ -192,6 +192,13 @@ package cachepool_pkg; // UART ID width, with an extra xbar localparam int unsigned SpatzAxiUartIdWidth = SpatzAxiNarrowIdWidth + $clog2(NumTiles); + // BootROM AXI ID width: wide data bus, muxed from NumTiles tile ports. + // The group's axi_mst_cache slave ID width = GroupAxiIdWidth + 1 + // (cluster passes WideIdWidthIn = SpatzAxiIdOutWidth - clog2(NumClusterMst) + // = ClusterAxiIdWidth + 1 - ClusterRouteIdWidth = GroupAxiIdWidth + 1). + // The mux master adds $clog2(NumTiles) bits on top. + localparam int unsigned BootRomAxiSlvIdWidth = GroupAxiIdWidth + 1 + $clog2(NumTiles); + /***** Tile Ports *****/ // We have three sets of AXI ports for each tile: // 1) Wide output bus for BootRom & L2 (from ICache) @@ -286,6 +293,8 @@ package cachepool_pkg; typedef logic [IwcAxiIdOutWidth-1:0] axi_id_out_iwc_t; + typedef logic [BootRomAxiSlvIdWidth-1:0] axi_bootrom_slv_id_t; + ////////////////// // TILE TYPES // ////////////////// @@ -424,9 +433,11 @@ package cachepool_pkg; `AXI_TYPEDEF_ALL(spatz_axi_out, axi_addr_t, axi_id_out_t, axi_wide_data_t, axi_wide_strb_t, axi_user_t) `AXI_TYPEDEF_ALL(spatz_axi_iwc_out, axi_addr_t, axi_id_out_iwc_t, axi_wide_data_t, axi_wide_strb_t, axi_user_t) - `AXI_TYPEDEF_ALL(axi_uart, axi_addr_t, axi_uart_id_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t) - `AXI_TYPEDEF_ALL(axi_csr_mst, axi_addr_t, axi_id_csr_mst_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t) - `AXI_TYPEDEF_ALL(axi_csr_slv, axi_addr_t, axi_id_csr_slv_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_uart, axi_addr_t, axi_uart_id_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_csr_mst, axi_addr_t, axi_id_csr_mst_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_csr_slv, axi_addr_t, axi_id_csr_slv_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t) + // BootROM: wide data bus (same payload as cache), slv = post-mux (widened ID) + `AXI_TYPEDEF_ALL(axi_bootrom_slv, axi_addr_t, axi_bootrom_slv_id_t, axi_wide_data_t, axi_wide_strb_t, axi_user_t) /************************************************************** * FUNCTIONS diff --git a/sim/scripts/vsim_cluster.tcl b/sim/scripts/vsim_cluster.tcl index c8d66f3..e34f008 100644 --- a/sim/scripts/vsim_cluster.tcl +++ b/sim/scripts/vsim_cluster.tcl @@ -7,10 +7,6 @@ onerror {resume} set cluster_path $1 -add wave -noupdate -group Cluster -group xbar -group req_xbar ${cluster_path}/i_cluster_xbar/i_req_xbar/* -add wave -noupdate -group Cluster -group xbar -group rsp_xbar ${cluster_path}/i_cluster_xbar/i_rsp_xbar/* -add wave -noupdate -group Cluster -group xbar ${cluster_path}/i_cluster_xbar/* - add wave -noupdate -group Cluster -group CSR ${cluster_path}/i_cachepool_cluster_peripheral/* add wave -noupdate -group Cluster -group Internal ${cluster_path}/* diff --git a/sim/scripts/vsim_group.tcl b/sim/scripts/vsim_group.tcl index 8edb7e5..f247f7e 100644 --- a/sim/scripts/vsim_group.tcl +++ b/sim/scripts/vsim_group.tcl @@ -16,4 +16,8 @@ for {set p 0} {$p < $2} {incr p} { add wave -noupdate -group Group -group remote_xbar[$p] ${xbar_path}/* } +add wave -noupdate -group Group -group refill_xbar -group req_xbar ${group_path}/i_refill_xbar/i_req_xbar/* +add wave -noupdate -group Group -group refill_xbar -group rsp_xbar ${group_path}/i_refill_xbar/i_rsp_xbar/* + + add wave -noupdate -group Group -group Internal ${group_path}/* diff --git a/util/auto-benchmark/write_results.py b/util/auto-benchmark/write_results.py index 4d254fe..2035e38 100644 --- a/util/auto-benchmark/write_results.py +++ b/util/auto-benchmark/write_results.py @@ -18,7 +18,7 @@ def extract_uart_lines(input_file_path, output_file_path, config=None, kernel=No # Copy only lines containing '[UART]' for line in input_file: - if '[UART]' in line: + if '[UART]' in line or '[EOC]' in line: output_file.write(line) output_file.write("\n----------------------------------------\n")