diff --git a/hw/vendor/cva6_cheri.lock.hjson b/hw/vendor/cva6_cheri.lock.hjson index cc672844..14d0a948 100644 --- a/hw/vendor/cva6_cheri.lock.hjson +++ b/hw/vendor/cva6_cheri.lock.hjson @@ -8,7 +8,7 @@ { upstream: { - url: https://github.com/Capabilities-Limited/cheri-cva6.git - rev: 8eae97cc21158bf5403f0984ef26318042285c54 + url: https://github.com/lowRISC/cva6-cheri.git + rev: 94a9d6f4eb2f7d59d9e66db7c39b522224312768 } } diff --git a/hw/vendor/cva6_cheri.vendor.hjson b/hw/vendor/cva6_cheri.vendor.hjson index b4668db1..fc8a7c82 100644 --- a/hw/vendor/cva6_cheri.vendor.hjson +++ b/hw/vendor/cva6_cheri.vendor.hjson @@ -4,11 +4,10 @@ { name: "cva6_cheri", target_dir: "cva6_cheri", - patch_dir: "patches/cva6_cheri", upstream: { - url: "https://github.com/Capabilities-Limited/cheri-cva6.git", - rev: "zcheri", + url: "https://github.com/lowRISC/cva6-cheri.git", + rev: "mocha", }, exclude_from_upstream: [ diff --git a/hw/vendor/patches/cva6_cheri/0001_Initial_Compilation_Fixes.patch b/hw/vendor/patches/cva6_cheri/0001_Initial_Compilation_Fixes.patch deleted file mode 100644 index 99e5d045..00000000 --- a/hw/vendor/patches/cva6_cheri/0001_Initial_Compilation_Fixes.patch +++ /dev/null @@ -1,409 +0,0 @@ -diff --git a/common/local/util/sram.sv b/common/local/util/sram.sv -index 8c6c0d3..62f7153 100644 ---- a/common/local/util/sram.sv -+++ b/common/local/util/sram.sv -@@ -64,42 +64,40 @@ end - - for (genvar k = 0; k<(DATA_WIDTH+63)/64; k++) begin : gen_cut - // unused byte-enable segments (8bits) are culled by the tool -- tc_sram_wrapper #( -- .NumWords(NUM_WORDS), // Number of Words in data array -- .DataWidth(64), // Data signal width -- .ByteWidth(32'd8), // Width of a data byte -- .NumPorts(32'd1), // Number of read and write ports -- .Latency(32'd1), // Latency when the read data is available -- .SimInit(SIM_INIT), // Simulation initialization -- .PrintSimCfg(1'b0) // Print configuration -+ prim_ram_1p #( -+ .Depth(NUM_WORDS), // Number of Words in data array -+ .Width(64), // Data signal width -+ .DataBitsPerMask(32'd8), // Width of a data byte -+ .MemInitFile(SIM_INIT) // Simulation initialization - ) i_tc_sram_wrapper ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .req_i ( req_i ), -- .we_i ( we_i ), -- .be_i ( be_aligned[k*8 +: 8] ), -+ .write_i ( we_i ), -+ .wmask_i ( be_aligned[k*8 +: 8] ), - .wdata_i ( wdata_aligned[k*64 +: 64] ), - .addr_i ( addr_i ), -- .rdata_o ( rdata_aligned[k*64 +: 64] ) -+ .rdata_o ( rdata_aligned[k*64 +: 64] ), -+ .cfg_i ( '0 ), -+ .cfg_rsp_o( ) - ); - if (USER_EN > 0) begin : gen_mem_user -- tc_sram_wrapper #( -- .NumWords(NUM_WORDS), // Number of Words in data array -- .DataWidth(64), // Data signal width -- .ByteWidth(32'd8), // Width of a data byte -- .NumPorts(32'd1), // Number of read and write ports -- .Latency(32'd1), // Latency when the read data is available -- .SimInit(SIM_INIT), // Simulation initialization -- .PrintSimCfg(1'b0) // Print configuration -+ prim_ram_1p #( -+ .Depth(NUM_WORDS), // Number of Words in data array -+ .Width(64), // Data signal width -+ .DataBitsPerMask(32'd8), // Width of a data byte -+ .MemInitFile(SIM_INIT) // Simulation initialization - ) i_tc_sram_wrapper_user ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .req_i ( req_i ), -- .we_i ( we_i ), -- .be_i ( be_aligned[k*8 +: 8] ), -+ .write_i ( we_i ), -+ .wmask_i ( be_aligned[k*8 +: 8] ), - .wdata_i ( wuser_aligned[k*64 +: 64] ), - .addr_i ( addr_i ), -- .rdata_o ( ruser_aligned[k*64 +: 64] ) -+ .rdata_o ( ruser_aligned[k*64 +: 64] ), -+ .cfg_i ( '0 ), -+ .cfg_rsp_o( ) - ); - end else begin : gen_mem_user - assign ruser_aligned[k*64 +: 64] = '0; -diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv -index c0a707c..ccdd0c0 100644 ---- a/core/acc_dispatcher.sv -+++ b/core/acc_dispatcher.sv -@@ -88,7 +88,7 @@ module acc_dispatcher - - `include "common_cells/registers.svh" - -- import cf_math_pkg::idx_width; -+ import prim_util_pkg::vbits; - - /*********************** - * Common signals * -@@ -102,7 +102,7 @@ module acc_dispatcher - **************************/ - - // Issue accelerator instructions -- `FF(acc_valid_q, acc_valid_d, '0) -+ `FF(acc_valid_q, acc_valid_d, '0, clk_i, rst_ni) - - assign acc_valid_ex_o = acc_valid_q; - assign acc_valid_d = ~issue_instr_i.ex.valid & -@@ -140,7 +140,7 @@ module acc_dispatcher - fu_data_t acc_insn_queue_o; - logic acc_insn_queue_pop; - logic acc_insn_queue_empty; -- logic [idx_width(InstructionQueueDepth)-1:0] acc_insn_queue_usage; -+ logic [vbits(InstructionQueueDepth)-1:0] acc_insn_queue_usage; - logic acc_commit; - logic [ CVA6Cfg.TRANS_ID_BITS-1:0] acc_commit_trans_id; - -@@ -174,13 +174,13 @@ module acc_dispatcher - - // Keep track of the instructions that were received by the dispatcher. - logic [CVA6Cfg.NR_SB_ENTRIES-1:0] insn_pending_d, insn_pending_q; -- `FF(insn_pending_q, insn_pending_d, '0) -+ `FF(insn_pending_q, insn_pending_d, '0, clk_i, rst_ni) - - // Only non-speculative instructions can be issued to the accelerators. - // The following block keeps track of which transaction IDs reached the - // top of the scoreboard, and are therefore no longer speculative. - logic [CVA6Cfg.NR_SB_ENTRIES-1:0] insn_ready_d, insn_ready_q; -- `FF(insn_ready_q, insn_ready_d, '0) -+ `FF(insn_ready_q, insn_ready_d, '0, clk_i, rst_ni) - - always_comb begin : p_non_speculative_ff - // Maintain state -@@ -261,7 +261,7 @@ module acc_dispatcher - ], - rs1 : acc_insn_queue_o.operand_a, - rs2 : acc_insn_queue_o.operand_b, -- frm : fpnew_pkg::roundmode_e'(fcsr_frm_i), -+ frm : 3'(fcsr_frm_i), - trans_id: acc_insn_queue_o.trans_id, - default: '0 - }; -@@ -334,7 +334,7 @@ module acc_dispatcher - // before continuing execution), halt execution while there are pending stores in - // the accelerator pipeline. - logic wait_acc_store_d, wait_acc_store_q; -- `FF(wait_acc_store_q, wait_acc_store_d, '0) -+ `FF(wait_acc_store_q, wait_acc_store_d, '0, clk_i, rst_ni) - - // Set on store barrier. Clear when no store is pending. - assign wait_acc_store_d = (wait_acc_store_q | commit_st_barrier_i) & acc_resp_i.acc_resp.store_pending; -diff --git a/core/cache_subsystem/cva6_icache.sv b/core/cache_subsystem/cva6_icache.sv -index f2ce1e4..c288275 100644 ---- a/core/cache_subsystem/cva6_icache.sv -+++ b/core/cache_subsystem/cva6_icache.sv -@@ -408,14 +408,19 @@ module cva6_icache - ); - - // generate random cacheline index -- lfsr #( -- .LfsrWidth(8), -- .OutWidth (CVA6Cfg.ICACHE_SET_ASSOC_WIDTH) -+ prim_lfsr #( -+ .LfsrDw (8), -+ .StateOutDw (CVA6Cfg.ICACHE_SET_ASSOC_WIDTH) - ) i_lfsr ( -- .clk_i (clk_i), -- .rst_ni(rst_ni), -- .en_i (update_lfsr), -- .out_o (rnd_way) -+ .clk_i (clk_i), -+ .rst_ni (rst_ni), -+ -+ .seed_en_i (1'b0), -+ .seed_i ('0), -+ .entropy_i ('0), -+ -+ .lfsr_en_i (update_lfsr), -+ .state_o (rnd_way) - ); - - -diff --git a/core/cache_subsystem/wt_dcache_mem.sv b/core/cache_subsystem/wt_dcache_mem.sv -index ad93dd2..af18ed6 100644 ---- a/core/cache_subsystem/wt_dcache_mem.sv -+++ b/core/cache_subsystem/wt_dcache_mem.sv -@@ -283,7 +283,7 @@ module wt_dcache_mem - // In case of an uncached read, return the desired CVA6Cfg.XLEN-bit segment of the most recent AXI read - assign wr_cl_off = (wr_cl_nc_i) ? (CVA6Cfg.AxiDataWidth == CVA6Cfg.CLEN) ? '0 : - (CVA6Cfg.CheriPresent) ? {{CVA6Cfg.DCACHE_OFFSET_WIDTH-CVA6Cfg.CLEN_ALIGN_BYTES{1'b0}}, wr_cl_off_i[CVA6Cfg.CLEN_ALIGN_BYTES]} : -- {{CVA6Cfg.DCACHE_OFFSET_WIDTH-AXI_OFFSET_WIDTH{1'b0}}, wr_cl_off_i[AXI_OFFSET_WIDTH-1:CVA6Cfg.CLEN_ALIGN_BYTES]} : -+ {{CVA6Cfg.DCACHE_OFFSET_WIDTH-AXI_OFFSET_WIDTH{1'b0}}, wr_cl_off_i[AXI_OFFSET_WIDTH-1-:CVA6Cfg.CLEN_ALIGN_BYTES]} : - wr_cl_off_i[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:CVA6Cfg.CLEN_ALIGN_BYTES]; - end else begin : gen_piton_offset - assign wr_cl_off = wr_cl_off_i[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:3]; -diff --git a/core/cache_subsystem/wt_dcache_missunit.sv b/core/cache_subsystem/wt_dcache_missunit.sv -index 76e8db6..cdc7e9c 100644 ---- a/core/cache_subsystem/wt_dcache_missunit.sv -+++ b/core/cache_subsystem/wt_dcache_missunit.sv -@@ -198,14 +198,19 @@ module wt_dcache_missunit - ); - - // generate random cacheline index -- lfsr #( -- .LfsrWidth(8), -- .OutWidth (CVA6Cfg.DCACHE_SET_ASSOC_WIDTH) -+ prim_lfsr #( -+ .LfsrDw (8), -+ .StateOutDw (CVA6Cfg.DCACHE_SET_ASSOC_WIDTH) - ) i_lfsr_inv ( -- .clk_i (clk_i), -- .rst_ni(rst_ni), -- .en_i (update_lfsr), -- .out_o (rnd_way) -+ .clk_i (clk_i), -+ .rst_ni (rst_ni), -+ -+ .seed_en_i (1'b0), -+ .seed_i ('0), -+ .entropy_i ('0), -+ -+ .lfsr_en_i (update_lfsr), -+ .state_o (rnd_way) - ); - - assign repl_way = (all_ways_valid) ? rnd_way : inv_way; -@@ -329,7 +334,7 @@ module wt_dcache_missunit - logic [CVA6Cfg.CLEN_ALIGN_BYTES-1:0] amo_offset; - - if (CVA6Cfg.CheriPresent) begin -- assign amo_offset = ((amo_req_i.size==3'b011) & CVA6Cfg.IS_XLEN64 & CVA6Cfg.CheriPresent) ? amo_req_i.operand_a[CVA6Cfg.CLEN_ALIGN_BYTES-1:0] + 7 : -+ assign amo_offset = ((amo_req_i.size==3'b011) & CVA6Cfg.IS_XLEN64 & CVA6Cfg.CheriPresent) ? amo_req_i.operand_a[CVA6Cfg.CLEN_ALIGN_BYTES-1:0] + 7 : - ((amo_req_i.size==3'b010) & CVA6Cfg.IS_XLEN64) ? amo_req_i.operand_a[CVA6Cfg.CLEN_ALIGN_BYTES-1:0] + 3 : - ((amo_req_i.size==3'b001)) ? amo_req_i.operand_a[CVA6Cfg.CLEN_ALIGN_BYTES-1:0] + 1 : - amo_req_i.operand_a[CVA6Cfg.CLEN_ALIGN_BYTES-1:0]; -diff --git a/core/cva6_mmu/cva6_shared_tlb.sv b/core/cva6_mmu/cva6_shared_tlb.sv -index d7cfbfe..ca0f02f 100644 ---- a/core/cva6_mmu/cva6_shared_tlb.sv -+++ b/core/cva6_mmu/cva6_shared_tlb.sv -@@ -433,14 +433,19 @@ module cva6_shared_tlb #( - .empty_o(all_ways_valid) - ); - -- lfsr #( -- .LfsrWidth(8), -- .OutWidth ($clog2(SHARED_TLB_WAYS)) -+ prim_lfsr #( -+ .LfsrDw ( 8 ), -+ .StateOutDw ( $clog2(SHARED_TLB_WAYS) ) - ) i_lfsr ( -- .clk_i (clk_i), -- .rst_ni(rst_ni), -- .en_i (update_lfsr), -- .out_o (rnd_way) -+ .clk_i (clk_i), -+ .rst_ni (rst_ni), -+ -+ .seed_en_i (1'b0), -+ .seed_i ('0), -+ .entropy_i ('0), -+ -+ .lfsr_en_i (update_lfsr), -+ .state_o (rnd_way) - ); - - /////////////////////////////////////////////////////// -diff --git a/core/ex_stage.sv b/core/ex_stage.sv -index 61550f5..10f96ad 100644 ---- a/core/ex_stage.sv -+++ b/core/ex_stage.sv -@@ -308,10 +308,10 @@ module ex_stage - rs2_forwarding = rs2_forwarding_i[0]; - - if (CVA6Cfg.SuperscalarEn) begin -- if (one_cycle_select[1]) begin -- one_cycle_data = fu_data_i[1]; -- rs1_forwarding = rs1_forwarding_i[1]; -- rs2_forwarding = rs2_forwarding_i[1]; -+ if (one_cycle_select[CVA6Cfg.SuperscalarEn]) begin -+ one_cycle_data = fu_data_i[CVA6Cfg.SuperscalarEn]; -+ rs1_forwarding = rs1_forwarding_i[CVA6Cfg.SuperscalarEn]; -+ rs2_forwarding = rs2_forwarding_i[CVA6Cfg.SuperscalarEn]; - end - end - end -@@ -419,8 +419,8 @@ module ex_stage - always_comb begin - mult_data = mult_valid_i[0] ? fu_data_i[0] : '0; - if (CVA6Cfg.SuperscalarEn) begin -- if (mult_valid_i[1]) begin -- mult_data = fu_data_i[1]; -+ if (mult_valid_i[CVA6Cfg.SuperscalarEn]) begin -+ mult_data = fu_data_i[CVA6Cfg.SuperscalarEn]; - end - end - end -@@ -456,8 +456,8 @@ module ex_stage - always_comb begin - fpu_data = fpu_valid_i[0] ? fu_data_i[0] : '0; - if (CVA6Cfg.SuperscalarEn) begin -- if (fpu_valid_i[1]) begin -- fpu_data = fu_data_i[1]; -+ if (fpu_valid_i[CVA6Cfg.SuperscalarEn]) begin -+ fpu_data = fu_data_i[CVA6Cfg.SuperscalarEn]; - end - end - end -@@ -560,9 +560,9 @@ module ex_stage - lsu_tinst = tinst_i[0]; - - if (CVA6Cfg.SuperscalarEn) begin -- if (lsu_valid_i[1]) begin -- lsu_data = fu_data_i[1]; -- lsu_tinst = tinst_i[1]; -+ if (lsu_valid_i[CVA6Cfg.SuperscalarEn]) begin -+ lsu_data = fu_data_i[CVA6Cfg.SuperscalarEn]; -+ lsu_tinst = tinst_i[CVA6Cfg.SuperscalarEn]; - end - end - end -@@ -654,8 +654,8 @@ module ex_stage - always_comb begin - cvxif_data = x_valid_i[0] ? fu_data_i[0] : '0; - if (CVA6Cfg.SuperscalarEn) begin -- if (x_valid_i[1]) begin -- cvxif_data = fu_data_i[1]; -+ if (x_valid_i[CVA6Cfg.SuperscalarEn]) begin -+ cvxif_data = fu_data_i[CVA6Cfg.SuperscalarEn]; - end - end - end -diff --git a/core/frontend/instr_queue.sv b/core/frontend/instr_queue.sv -index 98b1481..7e9648b 100644 ---- a/core/frontend/instr_queue.sv -+++ b/core/frontend/instr_queue.sv -@@ -530,8 +530,8 @@ module instr_queue - .pop_i (pop_address) - ); - -- unread i_unread_branch_mask (.d_i(|branch_mask_extended)); -- unread i_unread_fifo_pos (.d_i(|fifo_pos_extended)); // we don't care about the lower signals -+ logic unused_branch_and_fifo; -+ assign unused_branch_and_fifo = |branch_mask_extended | |fifo_pos_extended; - - if (CVA6Cfg.RVC) begin : gen_pc_q_with_c - always_ff @(posedge clk_i or negedge rst_ni) begin -diff --git a/core/id_stage.sv b/core/id_stage.sv -index e819ffa..05f9b77 100644 ---- a/core/id_stage.sv -+++ b/core/id_stage.sv -@@ -166,7 +166,7 @@ module id_stage #( - logic commit_redirect_q; - - assign int_mode_decode[0] = int_mode_q; -- for (genvar i = 1; i <= CVA6Cfg.NrIssuePorts; i++) begin -+ for (genvar i = 1; i < CVA6Cfg.NrIssuePorts; i++) begin - assign int_mode_decode[i] = int_mode_decode_o[i-1]; - end - -diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv -index 1dd5b39..a2ddc6e 100644 ---- a/core/include/ariane_pkg.sv -+++ b/core/include/ariane_pkg.sv -@@ -864,6 +864,7 @@ package ariane_pkg; - default: ; // Do nothing - endcase - end -+ default: return 16'b0; - endcase - return 16'b0; - endfunction -diff --git a/core/include/cv64a6_imafdchzcheri_sv39_config_pkg.sv b/core/include/cv64a6_imafdchzcheri_sv39_config_pkg.sv -index f0a32ae..3ca9969 100644 ---- a/core/include/cv64a6_imafdchzcheri_sv39_config_pkg.sv -+++ b/core/include/cv64a6_imafdchzcheri_sv39_config_pkg.sv -@@ -12,8 +12,8 @@ package cva6_config_pkg; - - localparam CVA6ConfigXlen = 64; - -- localparam CVA6ConfigRVF = 1; -- localparam CVA6ConfigRVD = 1; -+ localparam CVA6ConfigRVF = 0; -+ localparam CVA6ConfigRVD = 0; - localparam CVA6ConfigF16En = 0; - localparam CVA6ConfigF16AltEn = 0; - localparam CVA6ConfigF8En = 0; -@@ -32,7 +32,7 @@ package cva6_config_pkg; - localparam CVA6ConfigRVZcherihybrid = 1; - localparam CVA6ConfigCheriCapTagWidth = 1; - localparam CVA6ConfigRVFI_DII = 0; -- localparam CVA6ConfigDIIIDLEN = 0; -+ localparam CVA6ConfigDIIIDLEN = 1; - - localparam CVA6ConfigAxiIdWidth = 4; - localparam CVA6ConfigAxiAddrWidth = 64; -diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv -index 914272f..670d2c6 100644 ---- a/core/issue_read_operands.sv -+++ b/core/issue_read_operands.sv -@@ -693,10 +693,12 @@ module issue_read_operands - forward_rs2[0] = 1'b0; - stall_rs2[0] = 1'b0; - end -- if (OPERANDS_PER_INSTR == 3 && ~x_issue_resp_i.register_read[2]) begin -- forward_rs3[0] = 1'b0; -- stall_rs3[0] = 1'b0; -- end -+ //TODO if we ever need CvxifEn -+ //if (OPERANDS_PER_INSTR == 3 && ~x_issue_resp_i.register_read[2]) begin -+ // forward_rs3[0] = 1'b0; -+ // stall_rs3[0] = 1'b0; -+ //end -+ $error("CvxifEn not supported."); - end - stall_raw[0] = x_transaction_rejected ? 1'b0 : stall_rs1[0] || stall_rs2[0] || stall_rs3[0]; - end -diff --git a/core/store_unit.sv b/core/store_unit.sv -index 323fdf5..e55b925 100644 ---- a/core/store_unit.sv -+++ b/core/store_unit.sv -@@ -126,6 +126,7 @@ module store_unit - 4'b1101: data_tmp[CVA6Cfg.CLEN-1:CVA6Cfg.XLEN] = {data[23:0], data[63:24]}; - 4'b1110: data_tmp[CVA6Cfg.CLEN-1:CVA6Cfg.XLEN] = {data[15:0], data[63:16]}; - 4'b1111: data_tmp[CVA6Cfg.CLEN-1:CVA6Cfg.XLEN] = {data[7:0], data[63:8]}; -+ default: data_tmp[CVA6Cfg.CLEN-1:CVA6Cfg.XLEN] = '0; - endcase - end - if (CVA6Cfg.IS_XLEN64) begin diff --git a/hw/vendor/patches/cva6_cheri/0002_Compilation_Fixes.patch b/hw/vendor/patches/cva6_cheri/0002_Compilation_Fixes.patch deleted file mode 100644 index 2a269af9..00000000 --- a/hw/vendor/patches/cva6_cheri/0002_Compilation_Fixes.patch +++ /dev/null @@ -1,78 +0,0 @@ -diff --git a/common/local/util/sram.sv b/common/local/util/sram.sv -index 62f7153..2a02373 100644 ---- a/common/local/util/sram.sv -+++ b/common/local/util/sram.sv -@@ -23,7 +23,7 @@ module sram #( - parameter USER_WIDTH = 1, - parameter USER_EN = 0, - parameter NUM_WORDS = 1024, -- parameter SIM_INIT = "none", -+ parameter SIM_INIT = "", - parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2) - )( - input logic clk_i, -diff --git a/common/local/util/sram_cache.sv b/common/local/util/sram_cache.sv -index 7ca7559..01f90e6 100644 ---- a/common/local/util/sram_cache.sv -+++ b/common/local/util/sram_cache.sv -@@ -23,7 +23,7 @@ module sram_cache #( - parameter USER_WIDTH = 1, - parameter USER_EN = 0, - parameter NUM_WORDS = 1024, -- parameter SIM_INIT = "none", -+ parameter SIM_INIT = "", - parameter BYTE_ACCESS = 1, - parameter TECHNO_CUT = 0, - parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2) -diff --git a/core/cva6.sv b/core/cva6.sv -index 4522765..19dc069 100644 ---- a/core/cva6.sv -+++ b/core/cva6.sv -@@ -1438,7 +1438,7 @@ module cva6 - .clk_i (clk_i), - .rst_ni (rst_ni), - // I$ -- .icache_en_i (icache_en_csr), -+ .icache_en_i (1'b0), - .icache_flush_i (icache_flush_ctrl_cache), - .icache_miss_o (icache_miss_cache_perf), - .icache_areq_i (icache_areq_ex_cache), -@@ -1446,7 +1446,7 @@ module cva6 - .icache_dreq_i (icache_dreq_if_cache), - .icache_dreq_o (icache_dreq_cache_if), - // D$ -- .dcache_enable_i (dcache_en_csr_nbdcache), -+ .dcache_enable_i (1'b0), - .dcache_flush_i (dcache_flush_ctrl_cache), - .dcache_flush_ack_o(dcache_flush_ack_cache_ctrl), - // to commit stage -@@ -1810,7 +1810,8 @@ module cva6 - if (~rst_ni) begin - cycles <= 0; - end else begin -- byte mode = ""; -+ byte mode; -+ mode = ""; - if (CVA6Cfg.DebugEn && debug_mode) mode = "D"; - else begin - case (priv_lvl) -diff --git a/core/include/cv64a6_imafdchzcheri_sv39_config_pkg.sv b/core/include/cv64a6_imafdchzcheri_sv39_config_pkg.sv -index 3ca9969..683329b 100644 ---- a/core/include/cv64a6_imafdchzcheri_sv39_config_pkg.sv -+++ b/core/include/cv64a6_imafdchzcheri_sv39_config_pkg.sv -@@ -141,11 +141,11 @@ package cva6_config_pkg; - NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), - NonIdempotentLength: 1024'({64'b0, 64'b0}), - NrExecuteRegionRules: unsigned'(3), -- ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), -- ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), -+ ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h10_0000, 64'h0}), -+ ExecuteRegionLength: 1024'({64'h40000000, 64'h10_0000, 64'h1000}), - NrCachedRegionRules: unsigned'(1), -- CachedRegionAddrBase: 1024'({64'h8000_0000}), -- CachedRegionLength: 1024'({64'h40000000}), -+ CachedRegionAddrBase: 1024'({64'hE000_0000}), -+ CachedRegionLength: 1024'({64'h1000_0000}), - MaxOutstandingStores: unsigned'(7), - DebugEn: bit'(1), - AxiBurstWriteEn: bit'(1), diff --git a/hw/vendor/patches/cva6_cheri/0003_reuse.patch b/hw/vendor/patches/cva6_cheri/0003_reuse.patch deleted file mode 100644 index 36e27929..00000000 --- a/hw/vendor/patches/cva6_cheri/0003_reuse.patch +++ /dev/null @@ -1,130 +0,0 @@ -commit f331857948a8378334eefd2c407a4e5b86658f7c -Author: Alice Ziuziakowska -Date: Mon Dec 15 12:24:18 2025 +0000 - - REUSE patch - -diff --git a/config/gen_from_riscv_config/scripts/libs/utils.py b/config/gen_from_riscv_config/scripts/libs/utils.py -index 93a57452e..4e93487ee 100644 ---- a/config/gen_from_riscv_config/scripts/libs/utils.py -+++ b/config/gen_from_riscv_config/scripts/libs/utils.py -@@ -357,10 +357,12 @@ class RstAddressBlock(AddressBlockClass): - r.directive( - "..", - content=[ -+ # REUSE-IgnoreStart - "Copyright (c) 2024 OpenHW Group", - "Copyright (c) 2024 Thales", - "SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1", - "Author: Abdessamii Oukalrazqou", -+ # REUSE-IgnoreEnd - ], - ) - r.title(self.name) # Use the name of the addressBlock as title -@@ -487,10 +489,12 @@ class InstrstBlock(InstructionBlockClass): - r.directive( - "..", - content=[ -+ # REUSE-IgnoreStart - "Copyright (c) 2024 OpenHW Group", - "Copyright (c) 2024 Thales", - "SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1", - "Author: Abdessamii Oukalrazqou", -+ # REUSE-IgnoreEnd - ], - ) - r.title(self.name) # Use the name of the addressBlock as title -@@ -567,12 +571,14 @@ class AdocAddressBlock(AddressBlockClass): - regRV32List = [reg.RV32 for reg in registerlist] - regRV64List = [reg.RV64 for reg in registerlist] - -+ # REUSE-IgnoreStart - r += "////\n" - r += " Copyright (c) 2024 OpenHW Group\n" - r += " Copyright (c) 2024 Thales\n" - r += " SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1\n" - r += " Author: Abdessamii Oukalrazqou\n" - r += "////\n\n" -+ # REUSE-IgnoreEnd - - r += "=== %s\n\n"%self.name - r += "==== Conventions\n\n" -@@ -681,12 +687,14 @@ class InstadocBlock(InstructionBlockClass): - InstrDescrList = [reg.descr for reg in self.Instructionlist] - InstrExtList = [reg.Extension_Name for reg in self.Instructionlist] - -+ # REUSE-IgnoreStart - r += "////\n" - r += " Copyright (c) 2024 OpenHW Group\n" - r += " Copyright (c) 2024 Thales\n" - r += " SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1\n" - r += " Author: Abdessamii Oukalrazqou\n" - r += "////\n\n" -+ # REUSE-IgnoreEnd - - r += "=== %s\n\n"%self.name - r += "==== Instructions\n\n" -@@ -738,11 +746,13 @@ class InstmdBlock(InstructionBlockClass): - InstrDescrList = [reg.descr for reg in self.Instructionlist] - InstrExtList = [reg.Extension_Name for reg in self.Instructionlist] - licence = [ -+ # REUSE-IgnoreStart - "", -+ # REUSE-IgnoreEnd - ] - for l in licence: - self.mdFile.write(l + "\n") -@@ -847,11 +857,13 @@ class MdAddressBlock(AddressBlockClass): - ] - regPrivModeList = [reg.access for reg in registerlist if reg.RV32 | reg.RV64] - licence = [ -+ # REUSE-IgnoreStart - "", -+ # REUSE-IgnoreEnd - ] - for l in licence: - self.mdFile.write(l + "\n") -diff --git a/docs/scripts/parameters_extractor.py b/docs/scripts/parameters_extractor.py -index e5ef4dd76..cf308771e 100644 ---- a/docs/scripts/parameters_extractor.py -+++ b/docs/scripts/parameters_extractor.py -@@ -55,6 +55,7 @@ def writeout_parameter_table(fileout, parameters, module): - - with open(fileout, "w") as fout: - fout.write("..\n") -+ # REUSE-IgnoreStart - fout.write(" Copyright 2024 Thales DIS France SAS\n") - fout.write( - ' Licensed under the Solderpad Hardware License, Version 2.1 (the "License");\n' -@@ -67,6 +68,7 @@ def writeout_parameter_table(fileout, parameters, module): - " You may obtain a copy of the License at https://solderpad.org/licenses/\n\n" - ) - fout.write(" Original Author: Jean-Roch COULON - Thales\n\n") -+ # REUSE-IgnoreEnd - fout.write(f".. _{module}_PARAMETERS:\n\n") - fout.write(f".. list-table:: {module} parameter configuration\n") - fout.write(" :header-rows: 1\n") -@@ -84,6 +86,7 @@ def writeout_parameter_table_adoc(fileout, parameters, module): - - with open(fileout, "w") as fout: - fout.write("////\n") -+ # REUSE-IgnoreStart - fout.write(" Copyright 2024 Thales DIS France SAS\n") - fout.write( - ' Licensed under the Solderpad Hardware License, Version 2.1 (the "License");\n' -@@ -96,6 +99,7 @@ def writeout_parameter_table_adoc(fileout, parameters, module): - " You may obtain a copy of the License at https://solderpad.org/licenses/\n\n" - ) - fout.write(" Original Author: Jean-Roch COULON - Thales\n") -+ # REUSE-IgnoreEnd - fout.write("////\n\n") - - fout.write(f"[[{module}_PARAMETERS]]\n\n") diff --git a/hw/vendor/patches/cva6_cheri/0004_reuse.patch b/hw/vendor/patches/cva6_cheri/0004_reuse.patch deleted file mode 100644 index 65390bbe..00000000 --- a/hw/vendor/patches/cva6_cheri/0004_reuse.patch +++ /dev/null @@ -1,32 +0,0 @@ -commit 29298b809d12e5a5327ebdbc13d97909b7fa3362 -Author: Alice Ziuziakowska -Date: Mon Dec 15 12:24:08 2025 +0000 - - REUSE patch - - This is done as another patch as we need to include this REUSE - comment below, otherwise the diff file *itself* will be considered - as having an invalid license in the line where it removes the "+" - - REUSE-IgnoreStart - -diff --git a/docs/user_guide/cva6_ug_csr.adoc b/docs/user_guide/cva6_ug_csr.adoc -index a609e8341..05a90a164 100644 ---- a/docs/user_guide/cva6_ug_csr.adoc -+++ b/docs/user_guide/cva6_ug_csr.adoc -@@ -2,10 +2,11 @@ - - == License - --Copyright 2022 OpenHW Group and Thales + --Copyright 2018 ETH Zürich and University of Bologna + --SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + --Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file except in compliance with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at https://solderpad.org/licenses/SHL-2.1/[https://solderpad.org/licenses/SHL-2.1/]. + -+[%hardbreaks] -+Copyright 2022 OpenHW Group and Thales -+Copyright 2018 ETH Zürich and University of Bologna -+SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -+Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file except in compliance with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at https://solderpad.org/licenses/SHL-2.1/[https://solderpad.org/licenses/SHL-2.1/]. - Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - == Foreword diff --git a/hw/vendor/patches/cva6_cheri/0005_Memory_Map.patch b/hw/vendor/patches/cva6_cheri/0005_Memory_Map.patch deleted file mode 100644 index d3390c95..00000000 --- a/hw/vendor/patches/cva6_cheri/0005_Memory_Map.patch +++ /dev/null @@ -1,20 +0,0 @@ -diff --git a/core/include/cv64a6_imafdchzcheri_sv39_config_pkg.sv b/core/include/cv64a6_imafdchzcheri_sv39_config_pkg.sv -index 683329b..dfe479a 100644 ---- a/core/include/cv64a6_imafdchzcheri_sv39_config_pkg.sv -+++ b/core/include/cv64a6_imafdchzcheri_sv39_config_pkg.sv -@@ -141,11 +141,11 @@ package cva6_config_pkg; - NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), - NonIdempotentLength: 1024'({64'b0, 64'b0}), - NrExecuteRegionRules: unsigned'(3), -- ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h10_0000, 64'h0}), -- ExecuteRegionLength: 1024'({64'h40000000, 64'h10_0000, 64'h1000}), -+ ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1000_0000, 64'h2000_0000}), -+ ExecuteRegionLength: 1024'({64'h4000_0000, 64'h2_0000, 64'h1000}), - NrCachedRegionRules: unsigned'(1), -- CachedRegionAddrBase: 1024'({64'hE000_0000}), -- CachedRegionLength: 1024'({64'h1000_0000}), -+ CachedRegionAddrBase: 1024'({64'h8000_0000}), -+ CachedRegionLength: 1024'({64'h4000_0000}), - MaxOutstandingStores: unsigned'(7), - DebugEn: bit'(1), - AxiBurstWriteEn: bit'(1), diff --git a/hw/vendor/patches/cva6_cheri/0006_Cache_Capability_Read_Fix.patch b/hw/vendor/patches/cva6_cheri/0006_Cache_Capability_Read_Fix.patch deleted file mode 100644 index 8cf43a50..00000000 --- a/hw/vendor/patches/cva6_cheri/0006_Cache_Capability_Read_Fix.patch +++ /dev/null @@ -1,19 +0,0 @@ -diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv -index 8b2a0c0..4170969 100644 ---- a/core/cache_subsystem/wt_axi_adapter.sv -+++ b/core/cache_subsystem/wt_axi_adapter.sv -@@ -551,6 +551,14 @@ module wt_axi_adapter - end - end - end -+ // Fixup for this shift register which assumes all bursted reads are data cache line width. -+ // This is false when the data cache is disabled and CHERI capabilities are 128 bit, bus is 64 bit and data cahce line is 256 bit. -+ if (CVA6Cfg.CheriPresent && axi_rd_last) begin -+ for (int i = 1; i < CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth; i+=2) begin -+ dcache_rd_shift_d[i] = axi_rd_data; -+ dcache_rd_shift_user_d[i] = axi_rd_user; -+ end -+ end - end else if (CVA6Cfg.RVA && dcache_sc_rtrn) begin - // encode lr/sc success - dcache_rd_shift_d[0] = '0; diff --git a/hw/vendor/patches/cva6_cheri/0007_tag_data_sram_wmask.patch b/hw/vendor/patches/cva6_cheri/0007_tag_data_sram_wmask.patch deleted file mode 100644 index fb6d1ef1..00000000 --- a/hw/vendor/patches/cva6_cheri/0007_tag_data_sram_wmask.patch +++ /dev/null @@ -1,48 +0,0 @@ -diff --git a/common/local/util/sram.sv b/common/local/util/sram.sv -index 2a02373..e0df2b7 100644 ---- a/common/local/util/sram.sv -+++ b/common/local/util/sram.sv -@@ -47,6 +47,7 @@ logic [USER_WIDTH_ALIGNED-1:0] wuser_aligned; - logic [BE_WIDTH_ALIGNED-1:0] be_aligned; - logic [DATA_WIDTH_ALIGNED-1:0] rdata_aligned; - logic [USER_WIDTH_ALIGNED-1:0] ruser_aligned; -+logic [DATA_WIDTH_ALIGNED-1:0] wmask_aligned; - - - // align to 64 bits for inferrable macro below -@@ -54,10 +55,17 @@ always_comb begin : p_align - wdata_aligned ='0; - wuser_aligned ='0; - be_aligned ='0; -+ wmask_aligned ='0; - wdata_aligned[DATA_WIDTH-1:0] = wdata_i; - wuser_aligned[USER_WIDTH-1:0] = wuser_i; - be_aligned[BE_WIDTH_ALIGNED-1:0] = be_i; - -+ // Convert byte-enables (BE) to a bit-level write mask (wmask). Each bit in be_i is expanded -+ // to 8 bits to match the SRAM bitmask interface. -+ for (int i=0; i < (DATA_WIDTH_ALIGNED / 8); ++i) begin -+ wmask_aligned[i*8 +: 8] = {8{be_aligned[i]}}; -+ end -+ - rdata_o = rdata_aligned[DATA_WIDTH-1:0]; - ruser_o = ruser_aligned[USER_WIDTH-1:0]; - end -@@ -74,7 +82,7 @@ end - .rst_ni ( rst_ni ), - .req_i ( req_i ), - .write_i ( we_i ), -- .wmask_i ( be_aligned[k*8 +: 8] ), -+ .wmask_i ( wmask_aligned[k*64 +: 64] ), - .wdata_i ( wdata_aligned[k*64 +: 64] ), - .addr_i ( addr_i ), - .rdata_o ( rdata_aligned[k*64 +: 64] ), -@@ -92,7 +100,7 @@ end - .rst_ni ( rst_ni ), - .req_i ( req_i ), - .write_i ( we_i ), -- .wmask_i ( be_aligned[k*8 +: 8] ), -+ .wmask_i ( wmask_aligned[k*64 +: 64] ), - .wdata_i ( wuser_aligned[k*64 +: 64] ), - .addr_i ( addr_i ), - .rdata_o ( ruser_aligned[k*64 +: 64] ), diff --git a/hw/vendor/patches/cva6_cheri/0008_pull_down_no_mmu.patch b/hw/vendor/patches/cva6_cheri/0008_pull_down_no_mmu.patch deleted file mode 100644 index 4c72897d..00000000 --- a/hw/vendor/patches/cva6_cheri/0008_pull_down_no_mmu.patch +++ /dev/null @@ -1,19 +0,0 @@ -diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv -index e0e606e..5083a00 100644 ---- a/core/load_store_unit.sv -+++ b/core/load_store_unit.sv -@@ -382,12 +382,14 @@ module load_store_unit - assign dcache_req_ports_o[0].address_index = '0; - assign dcache_req_ports_o[0].address_tag = '0; - assign dcache_req_ports_o[0].data_wdata = '0; -+ assign dcache_req_ports_o[0].data_wuser = '0; - assign dcache_req_ports_o[0].data_req = 1'b0; - assign dcache_req_ports_o[0].data_be = '1; - assign dcache_req_ports_o[0].data_size = 2'b11; - assign dcache_req_ports_o[0].data_we = 1'b0; - assign dcache_req_ports_o[0].kill_req = '0; - assign dcache_req_ports_o[0].tag_valid = 1'b0; -+ assign dcache_req_ports_o[0].strip_tag = 1'b0; - - assign itlb_miss_o = 1'b0; - assign dtlb_miss_o = 1'b0; diff --git a/hw/vendor/patches/cva6_cheri/0009_fix_fsm_issue_strict_inf.patch b/hw/vendor/patches/cva6_cheri/0009_fix_fsm_issue_strict_inf.patch deleted file mode 100644 index df31270b..00000000 --- a/hw/vendor/patches/cva6_cheri/0009_fix_fsm_issue_strict_inf.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff --git a/core/id_stage.sv b/core/id_stage.sv -index 05f9b77..409e903 100644 ---- a/core/id_stage.sv -+++ b/core/id_stage.sv -@@ -472,7 +472,7 @@ module id_stage #( - if (commit_redirect_q) int_mode_d = int_mode_issue_i; - else if (mispredict_redirect_i) int_mode_d = int_mode_resolved_branch_i; - else begin -- for (int i = 0; i <= CVA6Cfg.NrIssuePorts; i++) begin -+ for (int i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin - if (fetch_entry_ready_o[i]) begin - int_mode_d = int_mode_decode_o[i]; - end