consider mentioning simulation tooling in hdl section

[proppy]

It would be nice if the Hardware Description Languages section mentioned simulating tooling like:

• iverilog
• gtkwave
• verilator

A few things that I wish I learned from the workshop rather that "discovering/googling" by myself:

• use iverilog as a linter (seems to be more pedantic that yosys).
• how to create testbench
• how to $monitor variable
• gotcha to create / optimize vhd files for gtkwave visualization
• trade off between verilator / iverilog.

That'd be especially to helpful in order for FPGA newcomer to map those tool to traditionally software development workflow (edit/compile/debug lifecycle).