In the "Turning code into gates" subsection of the "Background" section, you have a logic diagram that is supposed to be equivalent to the Verilog code directly above it. However, we might have spotted a typo here. In the Verilog code, counter[3] and counter[5] are XORed whereas in the logic diagram it looks like counter[1] and counter[3] are depicted instead. If this not an error, perhaps it should be mentioned where this difference stems from.
In the "Turning code into gates" subsection of the "Background" section, you have a logic diagram that is supposed to be equivalent to the Verilog code directly above it. However, we might have spotted a typo here. In the Verilog code, counter[3] and counter[5] are XORed whereas in the logic diagram it looks like counter[1] and counter[3] are depicted instead. If this not an error, perhaps it should be mentioned where this difference stems from.