From d67c55f843005fc089049fc0bbf245b6549d20a6 Mon Sep 17 00:00:00 2001 From: Changyuan Lyu Date: Sun, 19 Apr 2026 23:04:37 -0700 Subject: [PATCH] test: fix clippy warnings Signed-off-by: Changyuan Lyu --- .github/workflows/rust.yml | 2 +- alioth/src/device/cmos_test.rs | 4 +- alioth/src/device/console_test.rs | 4 +- alioth/src/device/fw_cfg/fw_cfg_test.rs | 2 +- alioth/src/device/ioapic_test.rs | 6 +- alioth/src/device/pl031_test.rs | 2 +- alioth/src/device/serial_test.rs | 9 +-- alioth/src/mem/emulated_test.rs | 19 +++---- alioth/src/pci/cap_test.rs | 24 ++++---- alioth/src/virtio/dev/entropy_test.rs | 12 ++-- alioth/src/virtio/dev/vsock/uds_vsock_test.rs | 22 +++---- alioth/src/virtio/queue/packed_test.rs | 57 ++++++++++--------- alioth/src/virtio/queue/queue_test.rs | 54 +++++++++--------- alioth/src/virtio/queue/split_test.rs | 42 +++++++------- alioth/src/virtio/virtio_test.rs | 5 +- 15 files changed, 130 insertions(+), 134 deletions(-) diff --git a/.github/workflows/rust.yml b/.github/workflows/rust.yml index b873de81..449d339a 100644 --- a/.github/workflows/rust.yml +++ b/.github/workflows/rust.yml @@ -69,7 +69,7 @@ jobs: --no-clean --workspace --ignore-filename-regex '.*_test.rs$' \ --lcov --output-path lcov-${{ matrix.target.name }}.info - name: Clippy - run: cargo clippy -- -D warnings + run: cargo clippy --all-targets -- -D warnings - name: Upload coverage report artifact uses: actions/upload-artifact@bbbca2ddaa5d8feaa63e36b76fdaad77386f024f # v7.0.0 with: diff --git a/alioth/src/device/cmos_test.rs b/alioth/src/device/cmos_test.rs index 7812dcee..91eea29c 100644 --- a/alioth/src/device/cmos_test.rs +++ b/alioth/src/device/cmos_test.rs @@ -22,7 +22,7 @@ use crate::mem::emulated::Mmio; #[test] fn test_cmos() { // Nov 7, 2025 at 15:44:58.01 GMT-08:00 - let now = DateTime::from_timestamp_nanos(1762559098010_000000); + let now = DateTime::from_timestamp_nanos(1_762_559_098_010_000_000); let cmos = Cmos::new(TestClock { now }); assert_eq!(cmos.size(), 2); @@ -70,7 +70,7 @@ fn test_cmos() { #[test] fn test_cmos_upgrade_in_progress() { // Nov 27, 2025 at 07:45:00.00 GMT-08:00 - let now = DateTime::from_timestamp_nanos(1764258300000_000000); + let now = DateTime::from_timestamp_nanos(1_764_258_300_000_000_000); let cmos = Cmos::new(TestClock { now }); assert_matches!(cmos.write(0x0, 1, 0xa), Ok(_)); diff --git a/alioth/src/device/console_test.rs b/alioth/src/device/console_test.rs index 3c89bcc3..a14c29e5 100644 --- a/alioth/src/device/console_test.rs +++ b/alioth/src/device/console_test.rs @@ -39,13 +39,13 @@ impl TestConsole { } } -impl<'a> Read for &'a TestConsole { +impl Read for &TestConsole { fn read(&mut self, buf: &mut [u8]) -> io::Result { Read::read(&mut *self.inbound.lock(), buf) } } -impl<'a> Write for &'a TestConsole { +impl Write for &TestConsole { fn write(&mut self, buf: &[u8]) -> io::Result { Write::write(&mut *self.outbound.lock(), buf) } diff --git a/alioth/src/device/fw_cfg/fw_cfg_test.rs b/alioth/src/device/fw_cfg/fw_cfg_test.rs index abe3858c..0c0afa20 100644 --- a/alioth/src/device/fw_cfg/fw_cfg_test.rs +++ b/alioth/src/device/fw_cfg/fw_cfg_test.rs @@ -78,7 +78,7 @@ fn test_fw_cfg_content_file_read() { #[case(FwCfgContent::Bytes(vec![0x01, 0x02, 0x03]), 2, &[0x03])] #[case(FwCfgContent::Bytes(vec![0x01, 0x02, 0x03]), 4, &[])] #[case(FwCfgContent::default(), 1, &[])] -#[case(FwCfgContent::Slice(b"abcd"), 0, &[b'a', b'b', b'c', b'd'])] +#[case(FwCfgContent::Slice(b"abcd"), 0, b"abcd")] #[case(FwCfgContent::Lu16(0xabcd_u16.into()), 0, &[0xcd, 0xab])] #[case(FwCfgContent::Lu16(0xabcd_u16.into()), 2, &[])] #[case(FwCfgContent::Lu32(0x1234_abcd_u32.into()), 0, &[0xcd, 0xab, 0x34, 0x12])] diff --git a/alioth/src/device/ioapic_test.rs b/alioth/src/device/ioapic_test.rs index 3f861650..a64c69ab 100644 --- a/alioth/src/device/ioapic_test.rs +++ b/alioth/src/device/ioapic_test.rs @@ -59,12 +59,10 @@ pub(crate) fn enable_pin(io_apci: &IoApic, pin: u8, vector: u8, let offset = 0x10 + (pin as u64 * 2); io_apci.write(IOREGSEL, 4, offset).unwrap(); io_apci - .write(IOWIN, 4, (redirtbl_entry.0 & 0xffffffff) as u64) + .write(IOWIN, 4, redirtbl_entry.0 & 0xffffffff) .unwrap(); io_apci.write(IOREGSEL, 4, offset + 1).unwrap(); - io_apci - .write(IOWIN, 4, (redirtbl_entry.0 >> 32) as u64) - .unwrap(); + io_apci.write(IOWIN, 4, redirtbl_entry.0 >> 32).unwrap(); } #[test] diff --git a/alioth/src/device/pl031_test.rs b/alioth/src/device/pl031_test.rs index d6af8e62..216cc80e 100644 --- a/alioth/src/device/pl031_test.rs +++ b/alioth/src/device/pl031_test.rs @@ -27,7 +27,7 @@ use crate::mem::emulated::Mmio; #[test] fn test_pl031() { // Nov 21, 2025 at 15:16:59 GMT-08:00 - let now = DateTime::from_timestamp_nanos(1763767019000_000000); + let now = DateTime::from_timestamp_nanos(1_763_767_019_000_000_000); let mut pl031 = Pl031::new(PL031_START, TestClock { now }); assert_eq!(pl031.size(), 0x1000); diff --git a/alioth/src/device/serial_test.rs b/alioth/src/device/serial_test.rs index e44dab9d..30c96115 100644 --- a/alioth/src/device/serial_test.rs +++ b/alioth/src/device/serial_test.rs @@ -31,6 +31,7 @@ use crate::device::serial::{ use crate::hv::tests::TestMsiSender; use crate::mem::emulated::Mmio; +#[allow(clippy::type_complexity)] fn fixture_serial() -> ( Serial, Arc>, @@ -58,12 +59,12 @@ fn test_serial_basic() { assert_matches!(serial.read(LINE_CONTROL_REGISTER, 1), Ok(0x83)); // Write divisor latches - assert_matches!(serial.write(DIVISOR_LATCH_LSB as u64, 1, 0x12), Ok(_)); - assert_matches!(serial.write(DIVISOR_LATCH_MSB as u64, 1, 0x34), Ok(_)); + assert_matches!(serial.write(DIVISOR_LATCH_LSB, 1, 0x12), Ok(_)); + assert_matches!(serial.write(DIVISOR_LATCH_MSB, 1, 0x34), Ok(_)); // Read divisor latches - assert_matches!(serial.read(DIVISOR_LATCH_LSB as u64, 1), Ok(0x12)); - assert_matches!(serial.read(DIVISOR_LATCH_MSB as u64, 1), Ok(0x34)); + assert_matches!(serial.read(DIVISOR_LATCH_LSB, 1), Ok(0x12)); + assert_matches!(serial.read(DIVISOR_LATCH_MSB, 1), Ok(0x34)); // Disable DLAB assert_matches!(serial.write(LINE_CONTROL_REGISTER, 1, 0x03), Ok(_)); diff --git a/alioth/src/mem/emulated_test.rs b/alioth/src/mem/emulated_test.rs index 5c10c0e7..cf0b9e3f 100644 --- a/alioth/src/mem/emulated_test.rs +++ b/alioth/src/mem/emulated_test.rs @@ -15,7 +15,7 @@ use std::sync::Arc; use parking_lot::Mutex; -use rstest::{fixture, rstest}; +use rstest::rstest; use super::{Action, Mmio, MmioBus}; use crate::mem::Result; @@ -51,7 +51,6 @@ impl Mmio for TestRange { // Creates a bus containing the following values: // | 0x01 | 0x23 | 0x67 0x45 | 0xef 0xcd 0xab 0x89 // | 0x34 0x12 0xcd 0xab -#[fixture] fn fixture_mmio_bus() -> MmioBus { let mut bus: MmioBus = MmioBus::new(); for (offset, size, val) in [ @@ -91,14 +90,10 @@ fn fixture_mmio_bus() -> MmioBus { #[case(0x8, 1, u64::MAX)] #[case(0xa, 8, u64::MAX)] #[case(0xe, 2, 0xabcd)] -fn test_mmio_bus_read( - fixture_mmio_bus: MmioBus, - #[case] addr: u64, - #[case] size: u8, - #[case] val: u64, -) { +fn test_mmio_bus_read(#[case] addr: u64, #[case] size: u8, #[case] val: u64) { + let mmio_bus = fixture_mmio_bus(); assert_eq!( - fixture_mmio_bus.read(addr, size).unwrap(), + mmio_bus.read(addr, size).unwrap(), val, "Read from addr {addr:#x} with size {size} failed" ) @@ -119,12 +114,12 @@ fn test_mmio_bus_read( #[case(0x6, 4, 0xcd_ab98, 0xffff_00cd_ab98)] #[case(0x8, 1, 0xff, u64::MAX)] fn test_mmio_bus_write( - fixture_mmio_bus: MmioBus, #[case] addr: u64, #[case] size: u8, #[case] val: u64, #[case] expected: u64, ) { - assert!(fixture_mmio_bus.write(addr, size, val).is_ok()); - assert_eq!(fixture_mmio_bus.read(addr, 8).unwrap(), expected); + let mmio_bus = fixture_mmio_bus(); + assert!(mmio_bus.write(addr, size, val).is_ok()); + assert_eq!(mmio_bus.read(addr, 8).unwrap(), expected); } diff --git a/alioth/src/pci/cap_test.rs b/alioth/src/pci/cap_test.rs index 1684189a..7fc8adc3 100644 --- a/alioth/src/pci/cap_test.rs +++ b/alioth/src/pci/cap_test.rs @@ -86,9 +86,9 @@ fn test_msi_cap_mmio_32() { assert_matches!(msi_cap.write(0x2, 2, ctrl.0 as u64), Ok(_)); assert_matches!(msi_cap.read(2, 2), Ok(v) => { let ctrl = MsiMsgCtrl(v as u16); - assert_eq!(ctrl.enable(), true); + assert!(ctrl.enable()); assert_eq!(ctrl.multi_msg(), 3); - assert_eq!(ctrl.ext_msg_data(), false); + assert!(!ctrl.ext_msg_data()); }); assert_matches!(msi_cap.write(0x8, 4, 0xaa_cc00), Ok(_)); @@ -98,7 +98,7 @@ fn test_msi_cap_mmio_32() { assert_eq!(irqfd.get_addr_hi(), 0x0); assert_eq!(irqfd.get_addr_lo(), 0xc000_d000); assert_eq!(irqfd.get_data(), 0xcc00 + index as u32); - assert_eq!(irqfd.get_masked(), false); + assert!(!irqfd.get_masked()); } ctrl.set_enable(false); @@ -130,9 +130,9 @@ fn test_msi_cap_mmio_32_pvm() { assert_matches!(msi_cap.write(0x0, 4, (ctrl.0 as u64) << 16), Ok(_)); assert_matches!(msi_cap.read(2, 2), Ok(v) => { let ctrl = MsiMsgCtrl(v as u16); - assert_eq!(ctrl.enable(), true); + assert!(ctrl.enable()); assert_eq!(ctrl.multi_msg(), 3); - assert_eq!(ctrl.ext_msg_data(), false); + assert!(!ctrl.ext_msg_data()); }); assert_matches!(msi_cap.write(0x8, 4, 0xaa_cc00), Ok(_)); @@ -147,7 +147,7 @@ fn test_msi_cap_mmio_32_pvm() { assert_eq!(irqfd.get_addr_hi(), 0x0); assert_eq!(irqfd.get_addr_lo(), 0xc000_d000); assert_eq!(irqfd.get_data(), 0xcc00 + index as u32); - assert_eq!(irqfd.get_masked(), false); + assert!(!irqfd.get_masked()); } } @@ -173,9 +173,9 @@ fn test_msi_cap_mmio_64_pvm() { assert_matches!(msi_cap.write(0x2, 2, ctrl.0 as u64), Ok(_)); assert_matches!(msi_cap.read(2, 2), Ok(v) => { let ctrl = MsiMsgCtrl(v as u16); - assert_eq!(ctrl.enable(), true); + assert!(ctrl.enable()); assert_eq!(ctrl.multi_msg(), 3); - assert_eq!(ctrl.ext_msg_data(), true); + assert!(ctrl.ext_msg_data()); }); assert_matches!(msi_cap.write(0xc, 4, 0xaa_cc00), Ok(_)); @@ -189,7 +189,7 @@ fn test_msi_cap_mmio_64_pvm() { assert_eq!(irqfd.get_addr_hi(), 0x1); assert_eq!(irqfd.get_addr_lo(), 0xc000_d000); assert_eq!(irqfd.get_data(), 0xaa_cc00 + index as u32); - assert_eq!(irqfd.get_masked(), false); + assert!(!irqfd.get_masked()); } assert_matches!(msi_cap.reset(), Ok(_)); @@ -281,12 +281,12 @@ fn test_msix_table_mmio() { assert_matches!(table.read(8, 4), Ok(0xabcd)); assert_matches!(table.read(12, 4), Ok(0x0)); - assert_matches!(table.write(16 + 0, 4, 0xff00_0000), Ok(Action::None)); + assert_matches!(table.write(16, 4, 0xff00_0000), Ok(Action::None)); assert_matches!(table.write(16 + 4, 4, 0x01), Ok(Action::None)); assert_matches!(table.write(16 + 8, 4, 0xabcd), Ok(Action::None)); assert_matches!(table.write_val(16 + 12, 4, 0x0), Ok(true)); - assert_matches!(table.read(16 + 0, 4), Ok(0xff00_0000)); + assert_matches!(table.read(16, 4), Ok(0xff00_0000)); assert_matches!(table.read(16 + 4, 4), Ok(0x01)); assert_matches!(table.read(16 + 8, 4), Ok(0xabcd)); assert_matches!(table.read(16 + 12, 4), Ok(0x0)); @@ -326,7 +326,7 @@ fn test_pci_cap_list() { let cap_list = PciCapList::try_from(caps).unwrap(); - assert_eq!(cap_list.is_empty(), false); + assert!(!cap_list.is_empty()); assert_eq!(cap_list.size(), 4096); assert_matches!(cap_list.read(0x40, 1), Ok(0x11)); diff --git a/alioth/src/virtio/dev/entropy_test.rs b/alioth/src/virtio/dev/entropy_test.rs index 3418a954..3b616381 100644 --- a/alioth/src/virtio/dev/entropy_test.rs +++ b/alioth/src/virtio/dev/entropy_test.rs @@ -16,17 +16,15 @@ use std::ffi::CString; use std::fs::OpenOptions; use std::io::Write; use std::os::unix::fs::OpenOptionsExt; -use std::sync::{Arc, mpsc}; +use std::sync::Arc; use std::time::Duration; use assert_matches::assert_matches; use flume::TryRecvError; -use rstest::rstest; use tempfile::TempDir; use crate::ffi; use crate::mem::emulated::{Action, Mmio}; -use crate::mem::mapped::RamBus; use crate::virtio::dev::entropy::{EntropyConfig, EntropyParam}; use crate::virtio::dev::{DevParam, StartParam, Virtio, WakeEvent}; use crate::virtio::queue::QueueReg; @@ -46,11 +44,11 @@ fn entry_config_test() { assert_matches!(config.write(0, 1, 0), Ok(Action::None)); } -#[rstest] -fn entropy_test(fixture_ram_bus: RamBus, fixture_queues: Box<[QueueReg]>) { - let ram_bus = Arc::new(fixture_ram_bus); +#[test] +fn entropy_test() { + let ram_bus = Arc::new(fixture_ram_bus()); let ram = ram_bus.lock_layout(); - let regs: Arc<[QueueReg]> = Arc::from(fixture_queues); + let regs: Arc<[QueueReg]> = Arc::from(fixture_queues(1)); let mut guest_q = GuestQueue::new( SplitQueue::new(®s[0], &ram, false).unwrap().unwrap(), diff --git a/alioth/src/virtio/dev/vsock/uds_vsock_test.rs b/alioth/src/virtio/dev/vsock/uds_vsock_test.rs index 25fdb981..fdc7e136 100644 --- a/alioth/src/virtio/dev/vsock/uds_vsock_test.rs +++ b/alioth/src/virtio/dev/vsock/uds_vsock_test.rs @@ -15,17 +15,16 @@ use std::io::{BufRead, BufReader, ErrorKind, Read, Write}; use std::mem::size_of; use std::os::unix::net::{UnixListener, UnixStream}; -use std::sync::{Arc, mpsc}; +use std::sync::Arc; use std::time::Duration; use assert_matches::assert_matches; use flume::{Receiver, Sender, TryRecvError}; -use rstest::rstest; use tempfile::TempDir; use zerocopy::{FromBytes, FromZeros, IntoBytes}; use crate::mem::emulated::{Action, Mmio}; -use crate::mem::mapped::{Ram, RamBus}; +use crate::mem::mapped::Ram; use crate::sync::notifier::Notifier; use crate::virtio::dev::vsock::{ ShutdownFlag, UdsVsockParam, VSOCK_CID_HOST, VsockConfig, VsockFeature, VsockHeader, VsockOp, @@ -51,6 +50,7 @@ fn vsock_config_test() { assert_matches!(config.write(0, 8, 0), Ok(Action::None)); } +#[allow(clippy::too_many_arguments)] fn send_to_tx<'m, Q>( hdr: &VsockHeader, data: &[u8], @@ -98,19 +98,19 @@ fn send_to_tx<'m, Q>( assert_eq!(used.len, 0); } -#[rstest] -fn vsock_conn_test(fixture_ram_bus: RamBus, #[with(3)] fixture_queues: Box<[QueueReg]>) { - let ram_bus = Arc::new(fixture_ram_bus); +#[test] +fn vsock_conn_test() { + let ram_bus = Arc::new(fixture_ram_bus()); let ram = ram_bus.lock_layout(); - let regs: Arc<[QueueReg]> = Arc::from(fixture_queues); + let regs: Arc<[QueueReg]> = Arc::from(fixture_queues(3)); let reg_tx = ®s[VsockVirtq::TX.raw() as usize]; let reg_rx = ®s[VsockVirtq::RX.raw() as usize]; let mut rx_q = GuestQueue::new( - SplitQueue::new(reg_rx, &*ram, false).unwrap().unwrap(), + SplitQueue::new(reg_rx, &ram, false).unwrap().unwrap(), reg_rx, ); let mut tx_q = GuestQueue::new( - SplitQueue::new(reg_tx, &*ram, false).unwrap().unwrap(), + SplitQueue::new(reg_tx, &ram, false).unwrap().unwrap(), reg_tx, ); @@ -127,7 +127,7 @@ fn vsock_conn_test(fixture_ram_bus: RamBus, #[with(3)] fixture_queues: Box<[Queu assert_matches!(dev.id(), DeviceId::SOCKET); assert_eq!(dev.name(), "vsock"); assert_eq!(dev.num_queues(), 3); - assert_eq!(dev.config().guest_cid, GUEST_CID as u32); + assert_eq!(dev.config().guest_cid, GUEST_CID); assert_eq!( dev.feature(), VsockFeature::STREAM.bits() | FEATURE_BUILT_IN @@ -303,7 +303,7 @@ fn vsock_conn_test(fixture_ram_bus: RamBus, #[with(3)] fixture_queues: Box<[Queu false, ); let mut g2h_read_buf = vec![0; g2h_data.len()]; - h2g_stream.read(&mut g2h_read_buf).unwrap(); + let _ = h2g_stream.read(&mut g2h_read_buf).unwrap(); assert_eq!(String::from_utf8_lossy(&g2h_read_buf), g2h_data); // 3. Shutdown host-initiated connection diff --git a/alioth/src/virtio/queue/packed_test.rs b/alioth/src/virtio/queue/packed_test.rs index 45abaf83..a74e8180 100644 --- a/alioth/src/virtio/queue/packed_test.rs +++ b/alioth/src/virtio/queue/packed_test.rs @@ -18,10 +18,9 @@ use std::sync::atomic::Ordering; use assert_matches::assert_matches; use rstest::rstest; -use crate::mem::mapped::RamBus; use crate::virtio::queue::packed::{DescEvent, EventFlag, PackedQueue, WrappedIndex}; use crate::virtio::queue::tests::{GuestQueue, UsedDesc, VirtQueueGuest}; -use crate::virtio::queue::{DescFlag, QueueReg, VirtQueue}; +use crate::virtio::queue::{DescFlag, VirtQueue}; use crate::virtio::tests::{DATA_ADDR, QUEUE_SIZE, fixture_queues, fixture_ram_bus}; const WRAP_COUNTER: u16 = 1 << 15; @@ -29,7 +28,7 @@ const WRAP_COUNTER: u16 = 1 << 15; #[rstest] #[case(3, 0, 1, 1)] #[case(5, 4, 4, WRAP_COUNTER | 3)] -#[case(3, WRAP_COUNTER | 0, 1, WRAP_COUNTER | 1)] +#[case(3, WRAP_COUNTER, 1, WRAP_COUNTER | 1)] #[case(5, WRAP_COUNTER | 4, 1, 0)] fn index_wrapping_add( #[case] size: u16, @@ -46,7 +45,7 @@ fn index_wrapping_add( #[rstest] #[case(3, 1, 1, 0)] #[case(5, WRAP_COUNTER | 3, 4, 4)] -#[case(3, WRAP_COUNTER | 1, 1, WRAP_COUNTER | 0)] +#[case(3, WRAP_COUNTER | 1, 1, WRAP_COUNTER)] #[case(5, 0, 1, WRAP_COUNTER | 4)] fn index_wrapping_sub( #[case] size: u16, @@ -118,21 +117,25 @@ impl<'m> VirtQueueGuest<'m> for PackedQueue<'m> { } } -#[rstest] -fn disabled_queue(fixture_ram_bus: RamBus, fixture_queues: Box<[QueueReg]>) { - let ram = fixture_ram_bus.lock_layout(); - let reg = &fixture_queues[0]; +#[test] +fn disabled_queue() { + let ram_bus = fixture_ram_bus(); + let queues = fixture_queues(1); + let ram = ram_bus.lock_layout(); + let reg = &queues[0]; reg.enabled.store(false, Ordering::Relaxed); - let split_queue = PackedQueue::new(reg, &*ram, false); + let split_queue = PackedQueue::new(reg, &ram, false); assert_matches!(split_queue, Ok(None)); } -#[rstest] -fn enabled_queue(fixture_ram_bus: RamBus, fixture_queues: Box<[QueueReg]>) { - let ram = fixture_ram_bus.lock_layout(); - let reg = &fixture_queues[0]; - let q = PackedQueue::new(reg, &*ram, false).unwrap().unwrap(); - let mut guest_q = GuestQueue::new(PackedQueue::new(reg, &*ram, false).unwrap().unwrap(), reg); +#[test] +fn enabled_queue() { + let ram_bus = fixture_ram_bus(); + let queues = fixture_queues(1); + let ram = ram_bus.lock_layout(); + let reg = &queues[0]; + let q = PackedQueue::new(reg, &ram, false).unwrap().unwrap(); + let mut guest_q = GuestQueue::new(PackedQueue::new(reg, &ram, false).unwrap().unwrap(), reg); let str_0 = "Hello, World!"; let str_1 = "Goodbye, World!"; @@ -186,11 +189,13 @@ fn enabled_queue(fixture_ram_bus: RamBus, fixture_queues: Box<[QueueReg]>) { assert_eq!(&b, str_2.as_bytes()); } -#[rstest] -fn enable_notification(fixture_ram_bus: RamBus, fixture_queues: Box<[QueueReg]>) { - let ram = fixture_ram_bus.lock_layout(); - let reg = &fixture_queues[0]; - let q = PackedQueue::new(reg, &*ram, false).unwrap().unwrap(); +#[test] +fn enable_notification() { + let ram_bus = fixture_ram_bus(); + let queues = fixture_queues(1); + let ram = ram_bus.lock_layout(); + let reg = &queues[0]; + let q = PackedQueue::new(reg, &ram, false).unwrap().unwrap(); q.enable_notification(false); assert_eq!(unsafe { &*q.notification }.flag, EventFlag::DISABLE); @@ -207,14 +212,12 @@ fn enable_notification(fixture_ram_bus: RamBus, fixture_queues: Box<[QueueReg]>) #[case(true, EventFlag::DESC, 0, 2, 1, false)] #[case(true, EventFlag::DESC, 0, 2, 2, true)] #[case(true, EventFlag::DESC, 0, 2, 3, true)] -#[case(true, EventFlag::DESC, WRAP_COUNTER | 0, 2, 3, false)] +#[case(true, EventFlag::DESC, WRAP_COUNTER, 2, 3, false)] #[case(true, EventFlag::DESC, WRAP_COUNTER | (QUEUE_SIZE - 1), 2, 2, false)] #[case(true, EventFlag::DESC, WRAP_COUNTER | (QUEUE_SIZE - 1), 2, 3, true)] #[case(true, EventFlag::DESC, QUEUE_SIZE - 1, WRAP_COUNTER | 1, 1, false)] #[case(true, EventFlag::DESC, QUEUE_SIZE - 1, WRAP_COUNTER | 1, 2, true)] fn is_interrupt_enabled( - fixture_ram_bus: RamBus, - fixture_queues: Box<[QueueReg]>, #[case] enable_event_idx: bool, #[case] event_flag: EventFlag, #[case] event_index: u16, @@ -222,9 +225,11 @@ fn is_interrupt_enabled( #[case] delta: u16, #[case] expected: bool, ) { - let ram = fixture_ram_bus.lock_layout(); - let reg = &fixture_queues[0]; - let q = PackedQueue::new(reg, &*ram, enable_event_idx) + let ram_bus = fixture_ram_bus(); + let queues = fixture_queues(1); + let ram = ram_bus.lock_layout(); + let reg = &queues[0]; + let q = PackedQueue::new(reg, &ram, enable_event_idx) .unwrap() .unwrap(); diff --git a/alioth/src/virtio/queue/queue_test.rs b/alioth/src/virtio/queue/queue_test.rs index 8a19ff34..242b9499 100644 --- a/alioth/src/virtio/queue/queue_test.rs +++ b/alioth/src/virtio/queue/queue_test.rs @@ -19,9 +19,7 @@ use std::sync::atomic::Ordering; use assert_matches::assert_matches; use flume::TryRecvError; -use rstest::rstest; -use crate::mem::mapped::RamBus; use crate::virtio::Error; use crate::virtio::queue::split::SplitQueue; use crate::virtio::queue::{ @@ -138,10 +136,7 @@ impl<'a> Read for Reader<'a> { return Ok(0); }; let mut buf = s.as_mut(); - loop { - let Some(data) = self.data.get(self.index) else { - break; - }; + while let Some(data) = self.data.get(self.index) { match data { ReaderData::Buf(data) => { let c = buf.write(&data[self.pos..]).unwrap(); @@ -151,7 +146,7 @@ impl<'a> Read for Reader<'a> { self.pos = 0; } count += c; - if buf.len() == 0 { + if buf.is_empty() { let Some(s) = buf_iter.next() else { break; }; @@ -171,16 +166,18 @@ impl<'a> Read for Reader<'a> { } } -#[rstest] -fn test_copy_from_reader(fixture_ram_bus: RamBus, fixture_queues: Box<[QueueReg]>) { - let ram = fixture_ram_bus.lock_layout(); - let reg = &fixture_queues[0]; +#[test] +fn test_copy_from_reader() { + let ram_bus = fixture_ram_bus(); + let queues = fixture_queues(1); + let ram = ram_bus.lock_layout(); + let reg = &queues[0]; let mut host_q = Queue::new( - SplitQueue::new(reg, &*ram, false).unwrap().unwrap(), + SplitQueue::new(reg, &ram, false).unwrap().unwrap(), reg, &ram, ); - let mut guest_q = GuestQueue::new(SplitQueue::new(reg, &*ram, false).unwrap().unwrap(), reg); + let mut guest_q = GuestQueue::new(SplitQueue::new(reg, &ram, false).unwrap().unwrap(), reg); assert!(ptr_eq(host_q.reg(), reg)); let (irq_tx, irq_rx) = flume::unbounded(); @@ -295,10 +292,7 @@ impl<'a> Write for Writer<'a> { return Ok(0); }; let mut buf = s.as_ref(); - loop { - let Some(data) = self.data.get_mut(self.index) else { - break; - }; + while let Some(data) = self.data.get_mut(self.index) { match data { WriterData::Buf(data) => { let c = buf.read(&mut data[self.pos..]).unwrap(); @@ -308,7 +302,7 @@ impl<'a> Write for Writer<'a> { self.pos = 0; } count += c; - if buf.len() == 0 { + if buf.is_empty() { let Some(s) = buf_iter.next() else { break; }; @@ -328,16 +322,18 @@ impl<'a> Write for Writer<'a> { } } -#[rstest] -fn test_copy_to_writer(fixture_ram_bus: RamBus, fixture_queues: Box<[QueueReg]>) { - let ram = fixture_ram_bus.lock_layout(); - let reg = &fixture_queues[0]; +#[test] +fn test_copy_to_writer() { + let ram_bus = fixture_ram_bus(); + let queues = fixture_queues(1); + let ram = ram_bus.lock_layout(); + let reg = &queues[0]; let mut host_q = Queue::new( - SplitQueue::new(reg, &*ram, false).unwrap().unwrap(), + SplitQueue::new(reg, &ram, false).unwrap().unwrap(), reg, &ram, ); - let mut guest_q = GuestQueue::new(SplitQueue::new(reg, &*ram, false).unwrap().unwrap(), reg); + let mut guest_q = GuestQueue::new(SplitQueue::new(reg, &ram, false).unwrap().unwrap(), reg); let (irq_tx, irq_rx) = flume::unbounded(); let irq_sender = FakeIrqSender { q_tx: irq_tx }; @@ -458,10 +454,12 @@ fn test_written_bytes() { assert_eq!(buf.as_slice(), str_1.as_bytes()); } -#[rstest] -fn test_handle_deferred(fixture_ram_bus: RamBus, fixture_queues: Box<[QueueReg]>) { - let ram = fixture_ram_bus.lock_layout(); - let reg = &fixture_queues[0]; +#[test] +fn test_handle_deferred() { + let ram_bus = fixture_ram_bus(); + let queues = fixture_queues(1); + let ram = ram_bus.lock_layout(); + let reg = &queues[0]; let mut host_q = Queue::new( SplitQueue::new(reg, &ram, false).unwrap().unwrap(), reg, diff --git a/alioth/src/virtio/queue/split_test.rs b/alioth/src/virtio/queue/split_test.rs index 3e91b1f9..51fcfd9d 100644 --- a/alioth/src/virtio/queue/split_test.rs +++ b/alioth/src/virtio/queue/split_test.rs @@ -16,12 +16,10 @@ use std::collections::HashMap; use std::sync::atomic::Ordering; use assert_matches::assert_matches; -use rstest::rstest; -use crate::mem::mapped::RamBus; +use crate::virtio::queue::VirtQueue; use crate::virtio::queue::split::{Desc, DescFlag, SplitQueue}; use crate::virtio::queue::tests::{GuestQueue, UsedDesc, VirtQueueGuest}; -use crate::virtio::queue::{QueueReg, VirtQueue}; use crate::virtio::tests::{DATA_ADDR, fixture_queues, fixture_ram_bus}; impl<'m> VirtQueueGuest<'m> for SplitQueue<'m> { @@ -71,21 +69,25 @@ impl<'m> VirtQueueGuest<'m> for SplitQueue<'m> { } } -#[rstest] -fn disabled_queue(fixture_ram_bus: RamBus, fixture_queues: Box<[QueueReg]>) { - let ram = fixture_ram_bus.lock_layout(); - let reg = &fixture_queues[0]; +#[test] +fn disabled_queue() { + let ram_bus = fixture_ram_bus(); + let queues = fixture_queues(1); + let ram = ram_bus.lock_layout(); + let reg = &queues[0]; reg.enabled.store(false, Ordering::Relaxed); - let split_queue = SplitQueue::new(reg, &*ram, false); + let split_queue = SplitQueue::new(reg, &ram, false); assert_matches!(split_queue, Ok(None)); } -#[rstest] -fn enabled_queue(fixture_ram_bus: RamBus, fixture_queues: Box<[QueueReg]>) { - let ram = fixture_ram_bus.lock_layout(); - let reg = &fixture_queues[0]; - let q = SplitQueue::new(reg, &*ram, false).unwrap().unwrap(); - let mut guest_q = GuestQueue::new(SplitQueue::new(reg, &*ram, false).unwrap().unwrap(), reg); +#[test] +fn enabled_queue() { + let ram_bus = fixture_ram_bus(); + let queues = fixture_queues(1); + let ram = ram_bus.lock_layout(); + let reg = &queues[0]; + let q = SplitQueue::new(reg, &ram, false).unwrap().unwrap(); + let mut guest_q = GuestQueue::new(SplitQueue::new(reg, &ram, false).unwrap().unwrap(), reg); let str_0 = "Hello, World!"; let str_1 = "Goodbye, World!"; @@ -130,11 +132,13 @@ fn enabled_queue(fixture_ram_bus: RamBus, fixture_queues: Box<[QueueReg]>) { assert_eq!(used.len, str_2.len() as u32); } -#[rstest] -fn event_idx_enabled(fixture_ram_bus: RamBus, fixture_queues: Box<[QueueReg]>) { - let ram = fixture_ram_bus.lock_layout(); - let reg = &fixture_queues[0]; - let q = SplitQueue::new(reg, &*ram, true).unwrap().unwrap(); +#[test] +fn event_idx_enabled() { + let ram_bus = fixture_ram_bus(); + let queues = fixture_queues(1); + let ram = ram_bus.lock_layout(); + let reg = &queues[0]; + let q = SplitQueue::new(reg, &ram, true).unwrap().unwrap(); unsafe { *q.used_event.unwrap() = 1 }; assert_eq!(q.used_event(), Some(1)); diff --git a/alioth/src/virtio/virtio_test.rs b/alioth/src/virtio/virtio_test.rs index 74e126f3..f40bed2f 100644 --- a/alioth/src/virtio/virtio_test.rs +++ b/alioth/src/virtio/virtio_test.rs @@ -16,7 +16,6 @@ use std::os::fd::{AsFd, BorrowedFd}; use std::sync::atomic::{AtomicBool, AtomicU16, AtomicU64}; use flume::Sender; -use rstest::fixture; use crate::hv::IoeventFd; use crate::mem::mapped::{ArcMemPages, RamBus}; @@ -28,7 +27,6 @@ const MEM_SIZE: usize = 2 << 20; pub const DATA_ADDR: u64 = 0x0; const QUEUE_START: u64 = 1 << 20; -#[fixture] pub fn fixture_ram_bus() -> RamBus { let host_pages = ArcMemPages::from_anonymous(MEM_SIZE, None, None).unwrap(); let ram_bus = RamBus::new(); @@ -36,8 +34,7 @@ pub fn fixture_ram_bus() -> RamBus { ram_bus } -#[fixture] -pub fn fixture_queues(#[default(1)] count: u16) -> Box<[QueueReg]> { +pub fn fixture_queues(count: u16) -> Box<[QueueReg]> { (0..count) .map(|i| { let base = QUEUE_START + i as u64 * 0x2000;