DMA cache coherency
It appears as though on all modern x86 CPUs DMA accesses are cache-coherent by design.
However I think it would be nice to not rely on this too much, and make it appear in the code
places where coherency between the CPU caches and the DMA device's view of memory
must be enforced.
This includes:
- flushing cache lines before sending data
- invalidating cache lines before reading received data
whether the operation results in a no-op depends on the target device.
Inspiration
- Linux's
dma_alloc_from_dev_coherent() and dma_map_single() API
Link
DMA cache coherency
It appears as though on all modern x86 CPUs DMA accesses are cache-coherent by design.
However I think it would be nice to not rely on this too much, and make it appear in the code
places where coherency between the CPU caches and the DMA device's view of memory
must be enforced.
This includes:
whether the operation results in a no-op depends on the target device.
Inspiration
dma_alloc_from_dev_coherent()anddma_map_single()APILink